Branch data Line data Source code
1 : : // SPDX-License-Identifier: GPL-2.0
2 : : /*
3 : : * This file contains work-arounds for many known PCI hardware bugs.
4 : : * Devices present only on certain architectures (host bridges et cetera)
5 : : * should be handled in arch-specific code.
6 : : *
7 : : * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 : : *
9 : : * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 : : *
11 : : * Init/reset quirks for USB host controllers should be in the USB quirks
12 : : * file, where their drivers can use them.
13 : : */
14 : :
15 : : #include <linux/types.h>
16 : : #include <linux/kernel.h>
17 : : #include <linux/export.h>
18 : : #include <linux/pci.h>
19 : : #include <linux/init.h>
20 : : #include <linux/delay.h>
21 : : #include <linux/acpi.h>
22 : : #include <linux/dmi.h>
23 : : #include <linux/ioport.h>
24 : : #include <linux/sched.h>
25 : : #include <linux/ktime.h>
26 : : #include <linux/mm.h>
27 : : #include <linux/nvme.h>
28 : : #include <linux/platform_data/x86/apple.h>
29 : : #include <linux/pm_runtime.h>
30 : : #include <linux/switchtec.h>
31 : : #include <asm/dma.h> /* isa_dma_bridge_buggy */
32 : : #include "pci.h"
33 : :
34 : 27 : static ktime_t fixup_debug_start(struct pci_dev *dev,
35 : : void (*fn)(struct pci_dev *dev))
36 : : {
37 [ - + ]: 27 : if (initcall_debug)
38 : 0 : pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
39 : :
40 : 27 : return ktime_get();
41 : : }
42 : :
43 : 27 : static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
44 : : void (*fn)(struct pci_dev *dev))
45 : : {
46 : 27 : ktime_t delta, rettime;
47 : 27 : unsigned long long duration;
48 : :
49 : 27 : rettime = ktime_get();
50 : 27 : delta = ktime_sub(rettime, calltime);
51 [ + - ]: 27 : duration = (unsigned long long) ktime_to_ns(delta) >> 10;
52 [ + - - + ]: 27 : if (initcall_debug || duration > 10000)
53 : 0 : pci_info(dev, "%pS took %lld usecs\n", fn, duration);
54 : 27 : }
55 : :
56 : 75 : static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
57 : : struct pci_fixup *end)
58 : : {
59 : 75 : ktime_t calltime;
60 : :
61 [ + + ]: 14718 : for (; f < end; f++)
62 [ + + + + ]: 14643 : if ((f->class == (u32) (dev->class >> f->class_shift) ||
63 : 12099 : f->class == (u32) PCI_ANY_ID) &&
64 [ + + + + ]: 12099 : (f->vendor == dev->vendor ||
65 : 3591 : f->vendor == (u16) PCI_ANY_ID) &&
66 [ + + + + ]: 3591 : (f->device == dev->device ||
67 : : f->device == (u16) PCI_ANY_ID)) {
68 : 27 : void (*hook)(struct pci_dev *dev);
69 : : #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
70 : 27 : hook = offset_to_ptr(&f->hook_offset);
71 : : #else
72 : : hook = f->hook;
73 : : #endif
74 : 27 : calltime = fixup_debug_start(dev, hook);
75 : 27 : hook(dev);
76 : 27 : fixup_debug_report(dev, calltime, hook);
77 : : }
78 : 75 : }
79 : :
80 : : extern struct pci_fixup __start_pci_fixups_early[];
81 : : extern struct pci_fixup __end_pci_fixups_early[];
82 : : extern struct pci_fixup __start_pci_fixups_header[];
83 : : extern struct pci_fixup __end_pci_fixups_header[];
84 : : extern struct pci_fixup __start_pci_fixups_final[];
85 : : extern struct pci_fixup __end_pci_fixups_final[];
86 : : extern struct pci_fixup __start_pci_fixups_enable[];
87 : : extern struct pci_fixup __end_pci_fixups_enable[];
88 : : extern struct pci_fixup __start_pci_fixups_resume[];
89 : : extern struct pci_fixup __end_pci_fixups_resume[];
90 : : extern struct pci_fixup __start_pci_fixups_resume_early[];
91 : : extern struct pci_fixup __end_pci_fixups_resume_early[];
92 : : extern struct pci_fixup __start_pci_fixups_suspend[];
93 : : extern struct pci_fixup __end_pci_fixups_suspend[];
94 : : extern struct pci_fixup __start_pci_fixups_suspend_late[];
95 : : extern struct pci_fixup __end_pci_fixups_suspend_late[];
96 : :
97 : : static bool pci_apply_fixup_final_quirks;
98 : :
99 : 96 : void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
100 : : {
101 : 96 : struct pci_fixup *start, *end;
102 : :
103 [ + + + - : 75 : switch (pass) {
- - - +
- ]
104 : : case pci_fixup_early:
105 : : start = __start_pci_fixups_early;
106 : : end = __end_pci_fixups_early;
107 : : break;
108 : :
109 : 21 : case pci_fixup_header:
110 : 21 : start = __start_pci_fixups_header;
111 : 21 : end = __end_pci_fixups_header;
112 : 21 : break;
113 : :
114 : 42 : case pci_fixup_final:
115 [ - + ]: 21 : if (!pci_apply_fixup_final_quirks)
116 : : return;
117 : : start = __start_pci_fixups_final;
118 : : end = __end_pci_fixups_final;
119 : : break;
120 : :
121 : 12 : case pci_fixup_enable:
122 : 12 : start = __start_pci_fixups_enable;
123 : 12 : end = __end_pci_fixups_enable;
124 : 12 : break;
125 : :
126 : 0 : case pci_fixup_resume:
127 : 0 : start = __start_pci_fixups_resume;
128 : 0 : end = __end_pci_fixups_resume;
129 : 0 : break;
130 : :
131 : 0 : case pci_fixup_resume_early:
132 : 0 : start = __start_pci_fixups_resume_early;
133 : 0 : end = __end_pci_fixups_resume_early;
134 : 0 : break;
135 : :
136 : 0 : case pci_fixup_suspend:
137 : 0 : start = __start_pci_fixups_suspend;
138 : 0 : end = __end_pci_fixups_suspend;
139 : 0 : break;
140 : :
141 : 0 : case pci_fixup_suspend_late:
142 : 0 : start = __start_pci_fixups_suspend_late;
143 : 0 : end = __end_pci_fixups_suspend_late;
144 : 0 : break;
145 : :
146 : : default:
147 : : /* stupid compiler warning, you would think with an enum... */
148 : : return;
149 : : }
150 : 75 : pci_do_fixups(dev, start, end);
151 : : }
152 : : EXPORT_SYMBOL(pci_fixup_device);
153 : :
154 : 3 : static int __init pci_apply_final_quirks(void)
155 : : {
156 : 3 : struct pci_dev *dev = NULL;
157 : 3 : u8 cls = 0;
158 : 3 : u8 tmp;
159 : :
160 [ - + ]: 3 : if (pci_cache_line_size)
161 : 0 : pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
162 : :
163 : 3 : pci_apply_fixup_final_quirks = true;
164 [ + + ]: 24 : for_each_pci_dev(dev) {
165 [ + - ]: 21 : pci_fixup_device(pci_fixup_final, dev);
166 : : /*
167 : : * If arch hasn't set it explicitly yet, use the CLS
168 : : * value shared by all PCI devices. If there's a
169 : : * mismatch, fall back to the default value.
170 : : */
171 [ + - ]: 21 : if (!pci_cache_line_size) {
172 : 21 : pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
173 [ + - ]: 21 : if (!cls)
174 : 21 : cls = tmp;
175 [ - + - - ]: 21 : if (!tmp || cls == tmp)
176 : 21 : continue;
177 : :
178 : 0 : pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
179 : : cls << 2, tmp << 2,
180 : : pci_dfl_cache_line_size << 2);
181 : 0 : pci_cache_line_size = pci_dfl_cache_line_size;
182 : : }
183 : : }
184 : :
185 [ + - ]: 3 : if (!pci_cache_line_size) {
186 : 3 : pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
187 : : pci_dfl_cache_line_size << 2);
188 [ + - ]: 3 : pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
189 : : }
190 : :
191 : 3 : return 0;
192 : : }
193 : : fs_initcall_sync(pci_apply_final_quirks);
194 : :
195 : : /*
196 : : * Decoding should be disabled for a PCI device during BAR sizing to avoid
197 : : * conflict. But doing so may cause problems on host bridge and perhaps other
198 : : * key system devices. For devices that need to have mmio decoding always-on,
199 : : * we need to set the dev->mmio_always_on bit.
200 : : */
201 : 3 : static void quirk_mmio_always_on(struct pci_dev *dev)
202 : : {
203 : 3 : dev->mmio_always_on = 1;
204 : 3 : }
205 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
206 : : PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
207 : :
208 : : /*
209 : : * The Mellanox Tavor device gives false positive parity errors. Mark this
210 : : * device with a broken_parity_status to allow PCI scanning code to "skip"
211 : : * this now blacklisted device.
212 : : */
213 : 0 : static void quirk_mellanox_tavor(struct pci_dev *dev)
214 : : {
215 : 0 : dev->broken_parity_status = 1; /* This device gives false positives */
216 : 0 : }
217 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
218 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
219 : :
220 : : /*
221 : : * Deal with broken BIOSes that neglect to enable passive release,
222 : : * which can cause problems in combination with the 82441FX/PPro MTRRs
223 : : */
224 : 3 : static void quirk_passive_release(struct pci_dev *dev)
225 : : {
226 : 3 : struct pci_dev *d = NULL;
227 : 3 : unsigned char dlc;
228 : :
229 : : /*
230 : : * We have to make sure a particular bit is set in the PIIX3
231 : : * ISA bridge, so we have to go out and find it.
232 : : */
233 [ + + ]: 6 : while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
234 : 3 : pci_read_config_byte(d, 0x82, &dlc);
235 [ + - ]: 3 : if (!(dlc & 1<<1)) {
236 : 3 : pci_info(d, "PIIX3: Enabling Passive Release\n");
237 : 3 : dlc |= 1<<1;
238 : 3 : pci_write_config_byte(d, 0x82, dlc);
239 : : }
240 : : }
241 : 3 : }
242 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
243 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
244 : :
245 : : /*
246 : : * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
247 : : * workaround but VIA don't answer queries. If you happen to have good
248 : : * contacts at VIA ask them for me please -- Alan
249 : : *
250 : : * This appears to be BIOS not version dependent. So presumably there is a
251 : : * chipset level fix.
252 : : */
253 : 3 : static void quirk_isa_dma_hangs(struct pci_dev *dev)
254 : : {
255 [ + - ]: 3 : if (!isa_dma_bridge_buggy) {
256 : 3 : isa_dma_bridge_buggy = 1;
257 : 3 : pci_info(dev, "Activating ISA DMA hang workarounds\n");
258 : : }
259 : 3 : }
260 : : /*
261 : : * It's not totally clear which chipsets are the problematic ones. We know
262 : : * 82C586 and 82C596 variants are affected.
263 : : */
264 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
265 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
266 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
267 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
268 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
269 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
270 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
271 : :
272 : : /*
273 : : * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
274 : : * for some HT machines to use C4 w/o hanging.
275 : : */
276 : 0 : static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
277 : : {
278 : 0 : u32 pmbase;
279 : 0 : u16 pm1a;
280 : :
281 : 0 : pci_read_config_dword(dev, 0x40, &pmbase);
282 : 0 : pmbase = pmbase & 0xff80;
283 : 0 : pm1a = inw(pmbase);
284 : :
285 [ # # ]: 0 : if (pm1a & 0x10) {
286 : 0 : pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
287 : 0 : outw(0x10, pmbase);
288 : : }
289 : 0 : }
290 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
291 : :
292 : : /* Chipsets where PCI->PCI transfers vanish or hang */
293 : 0 : static void quirk_nopcipci(struct pci_dev *dev)
294 : : {
295 [ # # ]: 0 : if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
296 : 0 : pci_info(dev, "Disabling direct PCI/PCI transfers\n");
297 : 0 : pci_pci_problems |= PCIPCI_FAIL;
298 : : }
299 : 0 : }
300 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
301 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
302 : :
303 : 0 : static void quirk_nopciamd(struct pci_dev *dev)
304 : : {
305 : 0 : u8 rev;
306 : 0 : pci_read_config_byte(dev, 0x08, &rev);
307 [ # # ]: 0 : if (rev == 0x13) {
308 : : /* Erratum 24 */
309 : 0 : pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
310 : 0 : pci_pci_problems |= PCIAGP_FAIL;
311 : : }
312 : 0 : }
313 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
314 : :
315 : : /* Triton requires workarounds to be used by the drivers */
316 : 0 : static void quirk_triton(struct pci_dev *dev)
317 : : {
318 [ # # ]: 0 : if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
319 : 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
320 : 0 : pci_pci_problems |= PCIPCI_TRITON;
321 : : }
322 : 0 : }
323 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
324 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
325 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
326 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
327 : :
328 : : /*
329 : : * VIA Apollo KT133 needs PCI latency patch
330 : : * Made according to a Windows driver-based patch by George E. Breese;
331 : : * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
332 : : * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
333 : : * which Mr Breese based his work.
334 : : *
335 : : * Updated based on further information from the site and also on
336 : : * information provided by VIA
337 : : */
338 : 0 : static void quirk_vialatency(struct pci_dev *dev)
339 : : {
340 : 0 : struct pci_dev *p;
341 : 0 : u8 busarb;
342 : :
343 : : /*
344 : : * Ok, we have a potential problem chipset here. Now see if we have
345 : : * a buggy southbridge.
346 : : */
347 : 0 : p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
348 [ # # ]: 0 : if (p != NULL) {
349 : :
350 : : /*
351 : : * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
352 : : * thanks Dan Hollis.
353 : : * Check for buggy part revisions
354 : : */
355 [ # # ]: 0 : if (p->revision < 0x40 || p->revision > 0x42)
356 : 0 : goto exit;
357 : : } else {
358 : 0 : p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
359 [ # # ]: 0 : if (p == NULL) /* No problem parts */
360 : 0 : goto exit;
361 : :
362 : : /* Check for buggy part revisions */
363 [ # # ]: 0 : if (p->revision < 0x10 || p->revision > 0x12)
364 : 0 : goto exit;
365 : : }
366 : :
367 : : /*
368 : : * Ok we have the problem. Now set the PCI master grant to occur
369 : : * every master grant. The apparent bug is that under high PCI load
370 : : * (quite common in Linux of course) you can get data loss when the
371 : : * CPU is held off the bus for 3 bus master requests. This happens
372 : : * to include the IDE controllers....
373 : : *
374 : : * VIA only apply this fix when an SB Live! is present but under
375 : : * both Linux and Windows this isn't enough, and we have seen
376 : : * corruption without SB Live! but with things like 3 UDMA IDE
377 : : * controllers. So we ignore that bit of the VIA recommendation..
378 : : */
379 : 0 : pci_read_config_byte(dev, 0x76, &busarb);
380 : :
381 : : /*
382 : : * Set bit 4 and bit 5 of byte 76 to 0x01
383 : : * "Master priority rotation on every PCI master grant"
384 : : */
385 : 0 : busarb &= ~(1<<5);
386 : 0 : busarb |= (1<<4);
387 : 0 : pci_write_config_byte(dev, 0x76, busarb);
388 : 0 : pci_info(dev, "Applying VIA southbridge workaround\n");
389 : 0 : exit:
390 : 0 : pci_dev_put(p);
391 : 0 : }
392 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
393 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
394 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
395 : : /* Must restore this on a resume from RAM */
396 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
397 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
398 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
399 : :
400 : : /* VIA Apollo VP3 needs ETBF on BT848/878 */
401 : 0 : static void quirk_viaetbf(struct pci_dev *dev)
402 : : {
403 [ # # ]: 0 : if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
404 : 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
405 : 0 : pci_pci_problems |= PCIPCI_VIAETBF;
406 : : }
407 : 0 : }
408 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
409 : :
410 : 0 : static void quirk_vsfx(struct pci_dev *dev)
411 : : {
412 [ # # ]: 0 : if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
413 : 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
414 : 0 : pci_pci_problems |= PCIPCI_VSFX;
415 : : }
416 : 0 : }
417 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
418 : :
419 : : /*
420 : : * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
421 : : * space. Latency must be set to 0xA and Triton workaround applied too.
422 : : * [Info kindly provided by ALi]
423 : : */
424 : 0 : static void quirk_alimagik(struct pci_dev *dev)
425 : : {
426 [ # # ]: 0 : if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
427 : 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
428 : 0 : pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
429 : : }
430 : 0 : }
431 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
432 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
433 : :
434 : : /* Natoma has some interesting boundary conditions with Zoran stuff at least */
435 : 3 : static void quirk_natoma(struct pci_dev *dev)
436 : : {
437 [ + - ]: 3 : if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
438 : 3 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
439 : 3 : pci_pci_problems |= PCIPCI_NATOMA;
440 : : }
441 : 3 : }
442 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
443 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
444 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
445 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
446 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
447 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
448 : :
449 : : /*
450 : : * This chip can cause PCI parity errors if config register 0xA0 is read
451 : : * while DMAs are occurring.
452 : : */
453 : 0 : static void quirk_citrine(struct pci_dev *dev)
454 : : {
455 : 0 : dev->cfg_size = 0xA0;
456 : 0 : }
457 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
458 : :
459 : : /*
460 : : * This chip can cause bus lockups if config addresses above 0x600
461 : : * are read or written.
462 : : */
463 : 0 : static void quirk_nfp6000(struct pci_dev *dev)
464 : : {
465 : 0 : dev->cfg_size = 0x600;
466 : 0 : }
467 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
468 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
469 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
470 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
471 : :
472 : : /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
473 : 0 : static void quirk_extend_bar_to_page(struct pci_dev *dev)
474 : : {
475 : 0 : int i;
476 : :
477 [ # # ]: 0 : for (i = 0; i < PCI_STD_NUM_BARS; i++) {
478 : 0 : struct resource *r = &dev->resource[i];
479 : :
480 [ # # # # ]: 0 : if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
481 : 0 : r->end = PAGE_SIZE - 1;
482 : 0 : r->start = 0;
483 : 0 : r->flags |= IORESOURCE_UNSET;
484 : 0 : pci_info(dev, "expanded BAR %d to page size: %pR\n",
485 : : i, r);
486 : : }
487 : : }
488 : 0 : }
489 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
490 : :
491 : : /*
492 : : * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
493 : : * If it's needed, re-allocate the region.
494 : : */
495 : 0 : static void quirk_s3_64M(struct pci_dev *dev)
496 : : {
497 : 0 : struct resource *r = &dev->resource[0];
498 : :
499 [ # # # # ]: 0 : if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
500 : 0 : r->flags |= IORESOURCE_UNSET;
501 : 0 : r->start = 0;
502 : 0 : r->end = 0x3ffffff;
503 : : }
504 : 0 : }
505 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
506 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
507 : :
508 : 0 : static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
509 : : const char *name)
510 : : {
511 : 0 : u32 region;
512 : 0 : struct pci_bus_region bus_region;
513 : 0 : struct resource *res = dev->resource + pos;
514 : :
515 : 0 : pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
516 : :
517 [ # # ]: 0 : if (!region)
518 : 0 : return;
519 : :
520 [ # # ]: 0 : res->name = pci_name(dev);
521 : 0 : res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
522 : 0 : res->flags |=
523 : : (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
524 : 0 : region &= ~(size - 1);
525 : :
526 : : /* Convert from PCI bus to resource space */
527 : 0 : bus_region.start = region;
528 : 0 : bus_region.end = region + size - 1;
529 : 0 : pcibios_bus_to_resource(dev->bus, res, &bus_region);
530 : :
531 : 0 : pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
532 : : name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
533 : : }
534 : :
535 : : /*
536 : : * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
537 : : * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
538 : : * BAR0 should be 8 bytes; instead, it may be set to something like 8k
539 : : * (which conflicts w/ BAR1's memory range).
540 : : *
541 : : * CS553x's ISA PCI BARs may also be read-only (ref:
542 : : * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
543 : : */
544 : 0 : static void quirk_cs5536_vsa(struct pci_dev *dev)
545 : : {
546 : 0 : static char *name = "CS5536 ISA bridge";
547 : :
548 [ # # # # : 0 : if (pci_resource_len(dev, 0) != 8) {
# # ]
549 : 0 : quirk_io(dev, 0, 8, name); /* SMB */
550 : 0 : quirk_io(dev, 1, 256, name); /* GPIO */
551 : 0 : quirk_io(dev, 2, 64, name); /* MFGPT */
552 : 0 : pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
553 : : name);
554 : : }
555 : 0 : }
556 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
557 : :
558 : 6 : static void quirk_io_region(struct pci_dev *dev, int port,
559 : : unsigned size, int nr, const char *name)
560 : : {
561 : 6 : u16 region;
562 : 6 : struct pci_bus_region bus_region;
563 : 6 : struct resource *res = dev->resource + nr;
564 : :
565 : 6 : pci_read_config_word(dev, port, ®ion);
566 : 6 : region &= ~(size - 1);
567 : :
568 [ - + ]: 6 : if (!region)
569 : 0 : return;
570 : :
571 [ + - ]: 6 : res->name = pci_name(dev);
572 : 6 : res->flags = IORESOURCE_IO;
573 : :
574 : : /* Convert from PCI bus to resource space */
575 : 6 : bus_region.start = region;
576 : 6 : bus_region.end = region + size - 1;
577 : 6 : pcibios_bus_to_resource(dev->bus, res, &bus_region);
578 : :
579 [ + - ]: 6 : if (!pci_claim_resource(dev, nr))
580 : 6 : pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
581 : : }
582 : :
583 : : /*
584 : : * ATI Northbridge setups MCE the processor if you even read somewhere
585 : : * between 0x3b0->0x3bb or read 0x3d3
586 : : */
587 : 0 : static void quirk_ati_exploding_mce(struct pci_dev *dev)
588 : : {
589 : 0 : pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
590 : : /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
591 : 0 : request_region(0x3b0, 0x0C, "RadeonIGP");
592 : 0 : request_region(0x3d3, 0x01, "RadeonIGP");
593 : 0 : }
594 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
595 : :
596 : : /*
597 : : * In the AMD NL platform, this device ([1022:7912]) has a class code of
598 : : * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
599 : : * claim it.
600 : : *
601 : : * But the dwc3 driver is a more specific driver for this device, and we'd
602 : : * prefer to use it instead of xhci. To prevent xhci from claiming the
603 : : * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
604 : : * defines as "USB device (not host controller)". The dwc3 driver can then
605 : : * claim it based on its Vendor and Device ID.
606 : : */
607 : 0 : static void quirk_amd_nl_class(struct pci_dev *pdev)
608 : : {
609 : 0 : u32 class = pdev->class;
610 : :
611 : : /* Use "USB Device (not host controller)" class */
612 : 0 : pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
613 : 0 : pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
614 : : class, pdev->class);
615 : 0 : }
616 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
617 : : quirk_amd_nl_class);
618 : :
619 : : /*
620 : : * Synopsys USB 3.x host HAPS platform has a class code of
621 : : * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
622 : : * devices should use dwc3-haps driver. Change these devices' class code to
623 : : * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
624 : : * them.
625 : : */
626 : 0 : static void quirk_synopsys_haps(struct pci_dev *pdev)
627 : : {
628 : 0 : u32 class = pdev->class;
629 : :
630 [ # # ]: 0 : switch (pdev->device) {
631 : 0 : case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
632 : : case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
633 : : case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
634 : 0 : pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
635 : 0 : pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
636 : : class, pdev->class);
637 : 0 : break;
638 : : }
639 : 0 : }
640 : : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
641 : : PCI_CLASS_SERIAL_USB_XHCI, 0,
642 : : quirk_synopsys_haps);
643 : :
644 : : /*
645 : : * Let's make the southbridge information explicit instead of having to
646 : : * worry about people probing the ACPI areas, for example.. (Yes, it
647 : : * happens, and if you read the wrong ACPI register it will put the machine
648 : : * to sleep with no way of waking it up again. Bummer).
649 : : *
650 : : * ALI M7101: Two IO regions pointed to by words at
651 : : * 0xE0 (64 bytes of ACPI registers)
652 : : * 0xE2 (32 bytes of SMB registers)
653 : : */
654 : 0 : static void quirk_ali7101_acpi(struct pci_dev *dev)
655 : : {
656 : 0 : quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
657 : 0 : quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
658 : 0 : }
659 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
660 : :
661 : 12 : static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
662 : : {
663 : 12 : u32 devres;
664 : 12 : u32 mask, size, base;
665 : :
666 : 12 : pci_read_config_dword(dev, port, &devres);
667 [ + - ]: 12 : if ((devres & enable) != enable)
668 : 12 : return;
669 : 0 : mask = (devres >> 16) & 15;
670 : 0 : base = devres & 0xffff;
671 : 0 : size = 16;
672 : 0 : for (;;) {
673 : 0 : unsigned bit = size >> 1;
674 [ # # ]: 0 : if ((bit & mask) == bit)
675 : : break;
676 : : size = bit;
677 : : }
678 : : /*
679 : : * For now we only print it out. Eventually we'll want to
680 : : * reserve it (at least if it's in the 0x1000+ range), but
681 : : * let's get enough confirmation reports first.
682 : : */
683 : 0 : base &= -size;
684 : 0 : pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
685 : : }
686 : :
687 : 0 : static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
688 : : {
689 : 0 : u32 devres;
690 : 0 : u32 mask, size, base;
691 : :
692 : 0 : pci_read_config_dword(dev, port, &devres);
693 [ # # ]: 0 : if ((devres & enable) != enable)
694 : 0 : return;
695 : 0 : base = devres & 0xffff0000;
696 : 0 : mask = (devres & 0x3f) << 16;
697 : 0 : size = 128 << 16;
698 : 0 : for (;;) {
699 : 0 : unsigned bit = size >> 1;
700 [ # # ]: 0 : if ((bit & mask) == bit)
701 : : break;
702 : : size = bit;
703 : : }
704 : :
705 : : /*
706 : : * For now we only print it out. Eventually we'll want to
707 : : * reserve it, but let's get enough confirmation reports first.
708 : : */
709 : 0 : base &= -size;
710 : 0 : pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
711 : : }
712 : :
713 : : /*
714 : : * PIIX4 ACPI: Two IO regions pointed to by longwords at
715 : : * 0x40 (64 bytes of ACPI registers)
716 : : * 0x90 (16 bytes of SMB registers)
717 : : * and a few strange programmable PIIX4 device resources.
718 : : */
719 : 3 : static void quirk_piix4_acpi(struct pci_dev *dev)
720 : : {
721 : 3 : u32 res_a;
722 : :
723 : 3 : quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
724 : 3 : quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
725 : :
726 : : /* Device resource A has enables for some of the other ones */
727 : 3 : pci_read_config_dword(dev, 0x5c, &res_a);
728 : :
729 : 3 : piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
730 : 3 : piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
731 : :
732 : : /* Device resource D is just bitfields for static resources */
733 : :
734 : : /* Device 12 enabled? */
735 [ - + ]: 3 : if (res_a & (1 << 29)) {
736 : 0 : piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
737 : 0 : piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
738 : : }
739 : : /* Device 13 enabled? */
740 [ - + ]: 3 : if (res_a & (1 << 30)) {
741 : 0 : piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
742 : 0 : piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
743 : : }
744 : 3 : piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
745 : 3 : piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
746 : 3 : }
747 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
748 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
749 : :
750 : : #define ICH_PMBASE 0x40
751 : : #define ICH_ACPI_CNTL 0x44
752 : : #define ICH4_ACPI_EN 0x10
753 : : #define ICH6_ACPI_EN 0x80
754 : : #define ICH4_GPIOBASE 0x58
755 : : #define ICH4_GPIO_CNTL 0x5c
756 : : #define ICH4_GPIO_EN 0x10
757 : : #define ICH6_GPIOBASE 0x48
758 : : #define ICH6_GPIO_CNTL 0x4c
759 : : #define ICH6_GPIO_EN 0x10
760 : :
761 : : /*
762 : : * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
763 : : * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
764 : : * 0x58 (64 bytes of GPIO I/O space)
765 : : */
766 : 0 : static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
767 : : {
768 : 0 : u8 enable;
769 : :
770 : : /*
771 : : * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
772 : : * with low legacy (and fixed) ports. We don't know the decoding
773 : : * priority and can't tell whether the legacy device or the one created
774 : : * here is really at that address. This happens on boards with broken
775 : : * BIOSes.
776 : : */
777 : 0 : pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
778 [ # # ]: 0 : if (enable & ICH4_ACPI_EN)
779 : 0 : quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
780 : : "ICH4 ACPI/GPIO/TCO");
781 : :
782 : 0 : pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
783 [ # # ]: 0 : if (enable & ICH4_GPIO_EN)
784 : 0 : quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
785 : : "ICH4 GPIO");
786 : 0 : }
787 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
788 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
789 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
790 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
791 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
792 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
793 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
794 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
795 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
796 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
797 : :
798 : 0 : static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
799 : : {
800 : 0 : u8 enable;
801 : :
802 : 0 : pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
803 [ # # ]: 0 : if (enable & ICH6_ACPI_EN)
804 : 0 : quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
805 : : "ICH6 ACPI/GPIO/TCO");
806 : :
807 : 0 : pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
808 [ # # ]: 0 : if (enable & ICH6_GPIO_EN)
809 : 0 : quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
810 : : "ICH6 GPIO");
811 : 0 : }
812 : :
813 : 0 : static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
814 : : const char *name, int dynsize)
815 : : {
816 : 0 : u32 val;
817 : 0 : u32 size, base;
818 : :
819 : 0 : pci_read_config_dword(dev, reg, &val);
820 : :
821 : : /* Enabled? */
822 [ # # ]: 0 : if (!(val & 1))
823 : 0 : return;
824 : 0 : base = val & 0xfffc;
825 [ # # ]: 0 : if (dynsize) {
826 : : /*
827 : : * This is not correct. It is 16, 32 or 64 bytes depending on
828 : : * register D31:F0:ADh bits 5:4.
829 : : *
830 : : * But this gets us at least _part_ of it.
831 : : */
832 : : size = 16;
833 : : } else {
834 : 0 : size = 128;
835 : : }
836 : 0 : base &= ~(size-1);
837 : :
838 : : /*
839 : : * Just print it out for now. We should reserve it after more
840 : : * debugging.
841 : : */
842 : 0 : pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
843 : : }
844 : :
845 : 0 : static void quirk_ich6_lpc(struct pci_dev *dev)
846 : : {
847 : : /* Shared ACPI/GPIO decode with all ICH6+ */
848 : 0 : ich6_lpc_acpi_gpio(dev);
849 : :
850 : : /* ICH6-specific generic IO decode */
851 : 0 : ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
852 : 0 : ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
853 : 0 : }
854 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
855 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
856 : :
857 : 0 : static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
858 : : const char *name)
859 : : {
860 : 0 : u32 val;
861 : 0 : u32 mask, base;
862 : :
863 : 0 : pci_read_config_dword(dev, reg, &val);
864 : :
865 : : /* Enabled? */
866 [ # # ]: 0 : if (!(val & 1))
867 : 0 : return;
868 : :
869 : : /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
870 : 0 : base = val & 0xfffc;
871 : 0 : mask = (val >> 16) & 0xfc;
872 : 0 : mask |= 3;
873 : :
874 : : /*
875 : : * Just print it out for now. We should reserve it after more
876 : : * debugging.
877 : : */
878 : 0 : pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
879 : : }
880 : :
881 : : /* ICH7-10 has the same common LPC generic IO decode registers */
882 : 0 : static void quirk_ich7_lpc(struct pci_dev *dev)
883 : : {
884 : : /* We share the common ACPI/GPIO decode with ICH6 */
885 : 0 : ich6_lpc_acpi_gpio(dev);
886 : :
887 : : /* And have 4 ICH7+ generic decodes */
888 : 0 : ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
889 : 0 : ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
890 : 0 : ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
891 : 0 : ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
892 : 0 : }
893 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
894 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
895 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
896 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
897 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
898 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
899 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
900 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
901 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
902 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
903 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
904 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
905 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
906 : :
907 : : /*
908 : : * VIA ACPI: One IO region pointed to by longword at
909 : : * 0x48 or 0x20 (256 bytes of ACPI registers)
910 : : */
911 : 0 : static void quirk_vt82c586_acpi(struct pci_dev *dev)
912 : : {
913 [ # # ]: 0 : if (dev->revision & 0x10)
914 : 0 : quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
915 : : "vt82c586 ACPI");
916 : 0 : }
917 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
918 : :
919 : : /*
920 : : * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
921 : : * 0x48 (256 bytes of ACPI registers)
922 : : * 0x70 (128 bytes of hardware monitoring register)
923 : : * 0x90 (16 bytes of SMB registers)
924 : : */
925 : 0 : static void quirk_vt82c686_acpi(struct pci_dev *dev)
926 : : {
927 : 0 : quirk_vt82c586_acpi(dev);
928 : :
929 : 0 : quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
930 : : "vt82c686 HW-mon");
931 : :
932 : 0 : quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
933 : 0 : }
934 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
935 : :
936 : : /*
937 : : * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
938 : : * 0x88 (128 bytes of power management registers)
939 : : * 0xd0 (16 bytes of SMB registers)
940 : : */
941 : 0 : static void quirk_vt8235_acpi(struct pci_dev *dev)
942 : : {
943 : 0 : quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
944 : 0 : quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
945 : 0 : }
946 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
947 : :
948 : : /*
949 : : * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
950 : : * back-to-back: Disable fast back-to-back on the secondary bus segment
951 : : */
952 : 0 : static void quirk_xio2000a(struct pci_dev *dev)
953 : : {
954 : 0 : struct pci_dev *pdev;
955 : 0 : u16 command;
956 : :
957 : 0 : pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
958 [ # # ]: 0 : list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
959 : 0 : pci_read_config_word(pdev, PCI_COMMAND, &command);
960 [ # # ]: 0 : if (command & PCI_COMMAND_FAST_BACK)
961 : 0 : pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
962 : : }
963 : 0 : }
964 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
965 : : quirk_xio2000a);
966 : :
967 : : #ifdef CONFIG_X86_IO_APIC
968 : :
969 : : #include <asm/io_apic.h>
970 : :
971 : : /*
972 : : * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
973 : : * devices to the external APIC.
974 : : *
975 : : * TODO: When we have device-specific interrupt routers, this code will go
976 : : * away from quirks.
977 : : */
978 : 0 : static void quirk_via_ioapic(struct pci_dev *dev)
979 : : {
980 : 0 : u8 tmp;
981 : :
982 [ # # ]: 0 : if (nr_ioapics < 1)
983 : : tmp = 0; /* nothing routed to external APIC */
984 : : else
985 : 0 : tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
986 : :
987 : 0 : pci_info(dev, "%sbling VIA external APIC routing\n",
988 : : tmp == 0 ? "Disa" : "Ena");
989 : :
990 : : /* Offset 0x58: External APIC IRQ output control */
991 : 0 : pci_write_config_byte(dev, 0x58, tmp);
992 : 0 : }
993 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
994 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
995 : :
996 : : /*
997 : : * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
998 : : * This leads to doubled level interrupt rates.
999 : : * Set this bit to get rid of cycle wastage.
1000 : : * Otherwise uncritical.
1001 : : */
1002 : 0 : static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1003 : : {
1004 : 0 : u8 misc_control2;
1005 : : #define BYPASS_APIC_DEASSERT 8
1006 : :
1007 : 0 : pci_read_config_byte(dev, 0x5B, &misc_control2);
1008 [ # # ]: 0 : if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1009 : 0 : pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1010 : 0 : pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1011 : : }
1012 : 0 : }
1013 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1014 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1015 : :
1016 : : /*
1017 : : * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1018 : : * We check all revs >= B0 (yet not in the pre production!) as the bug
1019 : : * is currently marked NoFix
1020 : : *
1021 : : * We have multiple reports of hangs with this chipset that went away with
1022 : : * noapic specified. For the moment we assume it's the erratum. We may be wrong
1023 : : * of course. However the advice is demonstrably good even if so.
1024 : : */
1025 : 0 : static void quirk_amd_ioapic(struct pci_dev *dev)
1026 : : {
1027 [ # # ]: 0 : if (dev->revision >= 0x02) {
1028 : 0 : pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1029 : 0 : pci_warn(dev, " : booting with the \"noapic\" option\n");
1030 : : }
1031 : 0 : }
1032 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1033 : : #endif /* CONFIG_X86_IO_APIC */
1034 : :
1035 : : #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1036 : :
1037 : : static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1038 : : {
1039 : : /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1040 : : if (dev->subsystem_device == 0xa118)
1041 : : dev->sriov->link = dev->devfn;
1042 : : }
1043 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1044 : : #endif
1045 : :
1046 : : /*
1047 : : * Some settings of MMRBC can lead to data corruption so block changes.
1048 : : * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1049 : : */
1050 : 0 : static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1051 : : {
1052 [ # # # # ]: 0 : if (dev->subordinate && dev->revision <= 0x12) {
1053 : 0 : pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1054 : : dev->revision);
1055 : 0 : dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1056 : : }
1057 : 0 : }
1058 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1059 : :
1060 : : /*
1061 : : * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1062 : : * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1063 : : * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1064 : : * of the ACPI SCI interrupt is only done for convenience.
1065 : : * -jgarzik
1066 : : */
1067 : 0 : static void quirk_via_acpi(struct pci_dev *d)
1068 : : {
1069 : 0 : u8 irq;
1070 : :
1071 : : /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1072 : 0 : pci_read_config_byte(d, 0x42, &irq);
1073 : 0 : irq &= 0xf;
1074 [ # # ]: 0 : if (irq && (irq != 2))
1075 : 0 : d->irq = irq;
1076 : 0 : }
1077 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1078 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1079 : :
1080 : : /* VIA bridges which have VLink */
1081 : : static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1082 : :
1083 : 0 : static void quirk_via_bridge(struct pci_dev *dev)
1084 : : {
1085 : : /* See what bridge we have and find the device ranges */
1086 [ # # # # : 0 : switch (dev->device) {
# ]
1087 : 0 : case PCI_DEVICE_ID_VIA_82C686:
1088 : : /*
1089 : : * The VT82C686 is special; it attaches to PCI and can have
1090 : : * any device number. All its subdevices are functions of
1091 : : * that single device.
1092 : : */
1093 : 0 : via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1094 : 0 : via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1095 : 0 : break;
1096 : 0 : case PCI_DEVICE_ID_VIA_8237:
1097 : : case PCI_DEVICE_ID_VIA_8237A:
1098 : 0 : via_vlink_dev_lo = 15;
1099 : 0 : break;
1100 : 0 : case PCI_DEVICE_ID_VIA_8235:
1101 : 0 : via_vlink_dev_lo = 16;
1102 : 0 : break;
1103 : 0 : case PCI_DEVICE_ID_VIA_8231:
1104 : : case PCI_DEVICE_ID_VIA_8233_0:
1105 : : case PCI_DEVICE_ID_VIA_8233A:
1106 : : case PCI_DEVICE_ID_VIA_8233C_0:
1107 : 0 : via_vlink_dev_lo = 17;
1108 : 0 : break;
1109 : : }
1110 : 0 : }
1111 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1112 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1113 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1114 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1115 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1116 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1117 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1118 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1119 : :
1120 : : /*
1121 : : * quirk_via_vlink - VIA VLink IRQ number update
1122 : : * @dev: PCI device
1123 : : *
1124 : : * If the device we are dealing with is on a PIC IRQ we need to ensure that
1125 : : * the IRQ line register which usually is not relevant for PCI cards, is
1126 : : * actually written so that interrupts get sent to the right place.
1127 : : *
1128 : : * We only do this on systems where a VIA south bridge was detected, and
1129 : : * only for VIA devices on the motherboard (see quirk_via_bridge above).
1130 : : */
1131 : 0 : static void quirk_via_vlink(struct pci_dev *dev)
1132 : : {
1133 : 0 : u8 irq, new_irq;
1134 : :
1135 : : /* Check if we have VLink at all */
1136 [ # # ]: 0 : if (via_vlink_dev_lo == -1)
1137 : 0 : return;
1138 : :
1139 : 0 : new_irq = dev->irq;
1140 : :
1141 : : /* Don't quirk interrupts outside the legacy IRQ range */
1142 [ # # ]: 0 : if (!new_irq || new_irq > 15)
1143 : : return;
1144 : :
1145 : : /* Internal device ? */
1146 [ # # # # ]: 0 : if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1147 [ # # ]: 0 : PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1148 : : return;
1149 : :
1150 : : /*
1151 : : * This is an internal VLink device on a PIC interrupt. The BIOS
1152 : : * ought to have set this but may not have, so we redo it.
1153 : : */
1154 : 0 : pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1155 [ # # ]: 0 : if (new_irq != irq) {
1156 : 0 : pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1157 : : irq, new_irq);
1158 : 0 : udelay(15); /* unknown if delay really needed */
1159 : 0 : pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1160 : : }
1161 : : }
1162 : : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1163 : :
1164 : : /*
1165 : : * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1166 : : * of VT82C597 for backward compatibility. We need to switch it off to be
1167 : : * able to recognize the real type of the chip.
1168 : : */
1169 : 0 : static void quirk_vt82c598_id(struct pci_dev *dev)
1170 : : {
1171 : 0 : pci_write_config_byte(dev, 0xfc, 0);
1172 : 0 : pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1173 : 0 : }
1174 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1175 : :
1176 : : /*
1177 : : * CardBus controllers have a legacy base address that enables them to
1178 : : * respond as i82365 pcmcia controllers. We don't want them to do this
1179 : : * even if the Linux CardBus driver is not loaded, because the Linux i82365
1180 : : * driver does not (and should not) handle CardBus.
1181 : : */
1182 : 0 : static void quirk_cardbus_legacy(struct pci_dev *dev)
1183 : : {
1184 : 0 : pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1185 : 0 : }
1186 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1187 : : PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1188 : : DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1189 : : PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1190 : :
1191 : : /*
1192 : : * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1193 : : * what the designers were smoking but let's not inhale...
1194 : : *
1195 : : * To be fair to AMD, it follows the spec by default, it's BIOS people who
1196 : : * turn it off!
1197 : : */
1198 : 0 : static void quirk_amd_ordering(struct pci_dev *dev)
1199 : : {
1200 : 0 : u32 pcic;
1201 : 0 : pci_read_config_dword(dev, 0x4C, &pcic);
1202 [ # # ]: 0 : if ((pcic & 6) != 6) {
1203 : 0 : pcic |= 6;
1204 : 0 : pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1205 : 0 : pci_write_config_dword(dev, 0x4C, pcic);
1206 : 0 : pci_read_config_dword(dev, 0x84, &pcic);
1207 : 0 : pcic |= (1 << 23); /* Required in this mode */
1208 : 0 : pci_write_config_dword(dev, 0x84, pcic);
1209 : : }
1210 : 0 : }
1211 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1212 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1213 : :
1214 : : /*
1215 : : * DreamWorks-provided workaround for Dunord I-3000 problem
1216 : : *
1217 : : * This card decodes and responds to addresses not apparently assigned to
1218 : : * it. We force a larger allocation to ensure that nothing gets put too
1219 : : * close to it.
1220 : : */
1221 : 0 : static void quirk_dunord(struct pci_dev *dev)
1222 : : {
1223 : 0 : struct resource *r = &dev->resource[1];
1224 : :
1225 : 0 : r->flags |= IORESOURCE_UNSET;
1226 : 0 : r->start = 0;
1227 : 0 : r->end = 0xffffff;
1228 : 0 : }
1229 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1230 : :
1231 : : /*
1232 : : * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1233 : : * decoding (transparent), and does indicate this in the ProgIf.
1234 : : * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1235 : : */
1236 : 0 : static void quirk_transparent_bridge(struct pci_dev *dev)
1237 : : {
1238 : 0 : dev->transparent = 1;
1239 : 0 : }
1240 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1241 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1242 : :
1243 : : /*
1244 : : * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1245 : : * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1246 : : * found at http://www.national.com/analog for info on what these bits do.
1247 : : * <christer@weinigel.se>
1248 : : */
1249 : 0 : static void quirk_mediagx_master(struct pci_dev *dev)
1250 : : {
1251 : 0 : u8 reg;
1252 : :
1253 : 0 : pci_read_config_byte(dev, 0x41, ®);
1254 [ # # ]: 0 : if (reg & 2) {
1255 : 0 : reg &= ~2;
1256 : 0 : pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1257 : : reg);
1258 : 0 : pci_write_config_byte(dev, 0x41, reg);
1259 : : }
1260 : 0 : }
1261 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1262 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1263 : :
1264 : : /*
1265 : : * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1266 : : * in the odd case it is not the results are corruption hence the presence
1267 : : * of a Linux check.
1268 : : */
1269 : 0 : static void quirk_disable_pxb(struct pci_dev *pdev)
1270 : : {
1271 : 0 : u16 config;
1272 : :
1273 [ # # ]: 0 : if (pdev->revision != 0x04) /* Only C0 requires this */
1274 : 0 : return;
1275 : 0 : pci_read_config_word(pdev, 0x40, &config);
1276 [ # # ]: 0 : if (config & (1<<6)) {
1277 : 0 : config &= ~(1<<6);
1278 : 0 : pci_write_config_word(pdev, 0x40, config);
1279 : 0 : pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1280 : : }
1281 : : }
1282 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1283 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1284 : :
1285 : 0 : static void quirk_amd_ide_mode(struct pci_dev *pdev)
1286 : : {
1287 : : /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1288 : 0 : u8 tmp;
1289 : :
1290 : 0 : pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1291 [ # # ]: 0 : if (tmp == 0x01) {
1292 : 0 : pci_read_config_byte(pdev, 0x40, &tmp);
1293 : 0 : pci_write_config_byte(pdev, 0x40, tmp|1);
1294 : 0 : pci_write_config_byte(pdev, 0x9, 1);
1295 : 0 : pci_write_config_byte(pdev, 0xa, 6);
1296 : 0 : pci_write_config_byte(pdev, 0x40, tmp);
1297 : :
1298 : 0 : pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1299 : 0 : pci_info(pdev, "set SATA to AHCI mode\n");
1300 : : }
1301 : 0 : }
1302 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1303 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1304 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1305 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1306 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1307 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1308 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1309 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1310 : :
1311 : : /* Serverworks CSB5 IDE does not fully support native mode */
1312 : 0 : static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1313 : : {
1314 : 0 : u8 prog;
1315 : 0 : pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1316 [ # # ]: 0 : if (prog & 5) {
1317 : 0 : prog &= ~5;
1318 : 0 : pdev->class &= ~5;
1319 : 0 : pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1320 : : /* PCI layer will sort out resources */
1321 : : }
1322 : 0 : }
1323 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1324 : :
1325 : : /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1326 : 0 : static void quirk_ide_samemode(struct pci_dev *pdev)
1327 : : {
1328 : 0 : u8 prog;
1329 : :
1330 : 0 : pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1331 : :
1332 [ # # ]: 0 : if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1333 : 0 : pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1334 : 0 : prog &= ~5;
1335 : 0 : pdev->class &= ~5;
1336 : 0 : pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1337 : : }
1338 : 0 : }
1339 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1340 : :
1341 : : /* Some ATA devices break if put into D3 */
1342 : 0 : static void quirk_no_ata_d3(struct pci_dev *pdev)
1343 : : {
1344 : 0 : pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1345 : 0 : }
1346 : : /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1347 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1348 : : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1349 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1350 : : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1351 : : /* ALi loses some register settings that we cannot then restore */
1352 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1353 : : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1354 : : /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1355 : : occur when mode detecting */
1356 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1357 : : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1358 : :
1359 : : /*
1360 : : * This was originally an Alpha-specific thing, but it really fits here.
1361 : : * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1362 : : */
1363 : 0 : static void quirk_eisa_bridge(struct pci_dev *dev)
1364 : : {
1365 : 0 : dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1366 : 0 : }
1367 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1368 : :
1369 : : /*
1370 : : * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1371 : : * is not activated. The myth is that Asus said that they do not want the
1372 : : * users to be irritated by just another PCI Device in the Win98 device
1373 : : * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1374 : : * package 2.7.0 for details)
1375 : : *
1376 : : * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1377 : : * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1378 : : * becomes necessary to do this tweak in two steps -- the chosen trigger
1379 : : * is either the Host bridge (preferred) or on-board VGA controller.
1380 : : *
1381 : : * Note that we used to unhide the SMBus that way on Toshiba laptops
1382 : : * (Satellite A40 and Tecra M2) but then found that the thermal management
1383 : : * was done by SMM code, which could cause unsynchronized concurrent
1384 : : * accesses to the SMBus registers, with potentially bad effects. Thus you
1385 : : * should be very careful when adding new entries: if SMM is accessing the
1386 : : * Intel SMBus, this is a very good reason to leave it hidden.
1387 : : *
1388 : : * Likewise, many recent laptops use ACPI for thermal management. If the
1389 : : * ACPI DSDT code accesses the SMBus, then Linux should not access it
1390 : : * natively, and keeping the SMBus hidden is the right thing to do. If you
1391 : : * are about to add an entry in the table below, please first disassemble
1392 : : * the DSDT and double-check that there is no code accessing the SMBus.
1393 : : */
1394 : : static int asus_hides_smbus;
1395 : :
1396 : 0 : static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1397 : : {
1398 [ # # ]: 0 : if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1399 [ # # ]: 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1400 [ # # ]: 0 : switch (dev->subsystem_device) {
1401 : 0 : case 0x8025: /* P4B-LX */
1402 : : case 0x8070: /* P4B */
1403 : : case 0x8088: /* P4B533 */
1404 : : case 0x1626: /* L3C notebook */
1405 : 0 : asus_hides_smbus = 1;
1406 : : }
1407 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1408 [ # # ]: 0 : switch (dev->subsystem_device) {
1409 : 0 : case 0x80b1: /* P4GE-V */
1410 : : case 0x80b2: /* P4PE */
1411 : : case 0x8093: /* P4B533-V */
1412 : 0 : asus_hides_smbus = 1;
1413 : : }
1414 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1415 [ # # ]: 0 : switch (dev->subsystem_device) {
1416 : 0 : case 0x8030: /* P4T533 */
1417 : 0 : asus_hides_smbus = 1;
1418 : : }
1419 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1420 [ # # ]: 0 : switch (dev->subsystem_device) {
1421 : 0 : case 0x8070: /* P4G8X Deluxe */
1422 : 0 : asus_hides_smbus = 1;
1423 : : }
1424 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1425 [ # # ]: 0 : switch (dev->subsystem_device) {
1426 : 0 : case 0x80c9: /* PU-DLS */
1427 : 0 : asus_hides_smbus = 1;
1428 : : }
1429 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1430 [ # # ]: 0 : switch (dev->subsystem_device) {
1431 : 0 : case 0x1751: /* M2N notebook */
1432 : : case 0x1821: /* M5N notebook */
1433 : : case 0x1897: /* A6L notebook */
1434 : 0 : asus_hides_smbus = 1;
1435 : : }
1436 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1437 [ # # ]: 0 : switch (dev->subsystem_device) {
1438 : 0 : case 0x184b: /* W1N notebook */
1439 : : case 0x186a: /* M6Ne notebook */
1440 : 0 : asus_hides_smbus = 1;
1441 : : }
1442 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1443 [ # # ]: 0 : switch (dev->subsystem_device) {
1444 : 0 : case 0x80f2: /* P4P800-X */
1445 : 0 : asus_hides_smbus = 1;
1446 : : }
1447 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1448 [ # # ]: 0 : switch (dev->subsystem_device) {
1449 : 0 : case 0x1882: /* M6V notebook */
1450 : : case 0x1977: /* A6VA notebook */
1451 : 0 : asus_hides_smbus = 1;
1452 : : }
1453 [ # # ]: 0 : } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1454 [ # # ]: 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1455 [ # # ]: 0 : switch (dev->subsystem_device) {
1456 : 0 : case 0x088C: /* HP Compaq nc8000 */
1457 : : case 0x0890: /* HP Compaq nc6000 */
1458 : 0 : asus_hides_smbus = 1;
1459 : : }
1460 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1461 [ # # ]: 0 : switch (dev->subsystem_device) {
1462 : 0 : case 0x12bc: /* HP D330L */
1463 : : case 0x12bd: /* HP D530 */
1464 : : case 0x006a: /* HP Compaq nx9500 */
1465 : 0 : asus_hides_smbus = 1;
1466 : : }
1467 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1468 [ # # ]: 0 : switch (dev->subsystem_device) {
1469 : 0 : case 0x12bf: /* HP xw4100 */
1470 : 0 : asus_hides_smbus = 1;
1471 : : }
1472 [ # # ]: 0 : } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1473 [ # # ]: 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1474 [ # # ]: 0 : switch (dev->subsystem_device) {
1475 : 0 : case 0xC00C: /* Samsung P35 notebook */
1476 : 0 : asus_hides_smbus = 1;
1477 : : }
1478 [ # # ]: 0 : } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1479 [ # # ]: 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1480 [ # # ]: 0 : switch (dev->subsystem_device) {
1481 : 0 : case 0x0058: /* Compaq Evo N620c */
1482 : 0 : asus_hides_smbus = 1;
1483 : : }
1484 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1485 [ # # ]: 0 : switch (dev->subsystem_device) {
1486 : 0 : case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1487 : : /* Motherboard doesn't have Host bridge
1488 : : * subvendor/subdevice IDs, therefore checking
1489 : : * its on-board VGA controller */
1490 : 0 : asus_hides_smbus = 1;
1491 : : }
1492 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1493 [ # # ]: 0 : switch (dev->subsystem_device) {
1494 : 0 : case 0x00b8: /* Compaq Evo D510 CMT */
1495 : : case 0x00b9: /* Compaq Evo D510 SFF */
1496 : : case 0x00ba: /* Compaq Evo D510 USDT */
1497 : : /* Motherboard doesn't have Host bridge
1498 : : * subvendor/subdevice IDs and on-board VGA
1499 : : * controller is disabled if an AGP card is
1500 : : * inserted, therefore checking USB UHCI
1501 : : * Controller #1 */
1502 : 0 : asus_hides_smbus = 1;
1503 : : }
1504 [ # # ]: 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1505 [ # # ]: 0 : switch (dev->subsystem_device) {
1506 : 0 : case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1507 : : /* Motherboard doesn't have host bridge
1508 : : * subvendor/subdevice IDs, therefore checking
1509 : : * its on-board VGA controller */
1510 : 0 : asus_hides_smbus = 1;
1511 : : }
1512 : : }
1513 : 0 : }
1514 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1515 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1516 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1517 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1518 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1519 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1520 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1521 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1522 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1523 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1524 : :
1525 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1526 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1527 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1528 : :
1529 : 0 : static void asus_hides_smbus_lpc(struct pci_dev *dev)
1530 : : {
1531 : 0 : u16 val;
1532 : :
1533 [ # # ]: 0 : if (likely(!asus_hides_smbus))
1534 : 0 : return;
1535 : :
1536 : 0 : pci_read_config_word(dev, 0xF2, &val);
1537 [ # # ]: 0 : if (val & 0x8) {
1538 : 0 : pci_write_config_word(dev, 0xF2, val & (~0x8));
1539 : 0 : pci_read_config_word(dev, 0xF2, &val);
1540 [ # # ]: 0 : if (val & 0x8)
1541 : 0 : pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1542 : : val);
1543 : : else
1544 : 0 : pci_info(dev, "Enabled i801 SMBus device\n");
1545 : : }
1546 : : }
1547 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1548 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1549 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1550 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1551 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1552 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1553 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1554 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1555 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1556 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1557 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1558 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1559 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1560 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1561 : :
1562 : : /* It appears we just have one such device. If not, we have a warning */
1563 : : static void __iomem *asus_rcba_base;
1564 : 0 : static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1565 : : {
1566 : 0 : u32 rcba;
1567 : :
1568 [ # # ]: 0 : if (likely(!asus_hides_smbus))
1569 : 0 : return;
1570 [ # # ]: 0 : WARN_ON(asus_rcba_base);
1571 : :
1572 : 0 : pci_read_config_dword(dev, 0xF0, &rcba);
1573 : : /* use bits 31:14, 16 kB aligned */
1574 : 0 : asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
1575 : 0 : if (asus_rcba_base == NULL)
1576 : 0 : return;
1577 : : }
1578 : :
1579 : 0 : static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1580 : : {
1581 : 0 : u32 val;
1582 : :
1583 [ # # # # : 0 : if (likely(!asus_hides_smbus || !asus_rcba_base))
# # ]
1584 : : return;
1585 : :
1586 : : /* read the Function Disable register, dword mode only */
1587 : 0 : val = readl(asus_rcba_base + 0x3418);
1588 : :
1589 : : /* enable the SMBus device */
1590 : 0 : writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1591 : : }
1592 : :
1593 : 0 : static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1594 : : {
1595 [ # # # # ]: 0 : if (likely(!asus_hides_smbus || !asus_rcba_base))
1596 : : return;
1597 : :
1598 : 0 : iounmap(asus_rcba_base);
1599 : 0 : asus_rcba_base = NULL;
1600 : 0 : pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1601 : : }
1602 : :
1603 : 0 : static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1604 : : {
1605 : 0 : asus_hides_smbus_lpc_ich6_suspend(dev);
1606 [ # # ]: 0 : asus_hides_smbus_lpc_ich6_resume_early(dev);
1607 : 0 : asus_hides_smbus_lpc_ich6_resume(dev);
1608 : 0 : }
1609 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1610 : : DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1611 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1612 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1613 : :
1614 : : /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1615 : 0 : static void quirk_sis_96x_smbus(struct pci_dev *dev)
1616 : : {
1617 : 0 : u8 val = 0;
1618 : 0 : pci_read_config_byte(dev, 0x77, &val);
1619 [ # # ]: 0 : if (val & 0x10) {
1620 : 0 : pci_info(dev, "Enabling SiS 96x SMBus\n");
1621 : 0 : pci_write_config_byte(dev, 0x77, val & ~0x10);
1622 : : }
1623 : 0 : }
1624 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1625 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1626 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1627 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1628 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1629 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1630 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1631 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1632 : :
1633 : : /*
1634 : : * ... This is further complicated by the fact that some SiS96x south
1635 : : * bridges pretend to be 85C503/5513 instead. In that case see if we
1636 : : * spotted a compatible north bridge to make sure.
1637 : : * (pci_find_device() doesn't work yet)
1638 : : *
1639 : : * We can also enable the sis96x bit in the discovery register..
1640 : : */
1641 : : #define SIS_DETECT_REGISTER 0x40
1642 : :
1643 : 0 : static void quirk_sis_503(struct pci_dev *dev)
1644 : : {
1645 : 0 : u8 reg;
1646 : 0 : u16 devid;
1647 : :
1648 : 0 : pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1649 : 0 : pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1650 : 0 : pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1651 [ # # # # ]: 0 : if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1652 : 0 : pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1653 : 0 : return;
1654 : : }
1655 : :
1656 : : /*
1657 : : * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1658 : : * it has already been processed. (Depends on link order, which is
1659 : : * apparently not guaranteed)
1660 : : */
1661 : 0 : dev->device = devid;
1662 : 0 : quirk_sis_96x_smbus(dev);
1663 : : }
1664 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1665 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1666 : :
1667 : : /*
1668 : : * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1669 : : * and MC97 modem controller are disabled when a second PCI soundcard is
1670 : : * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1671 : : * -- bjd
1672 : : */
1673 : 0 : static void asus_hides_ac97_lpc(struct pci_dev *dev)
1674 : : {
1675 : 0 : u8 val;
1676 : 0 : int asus_hides_ac97 = 0;
1677 : :
1678 [ # # ]: 0 : if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1679 [ # # ]: 0 : if (dev->device == PCI_DEVICE_ID_VIA_8237)
1680 : 0 : asus_hides_ac97 = 1;
1681 : : }
1682 : :
1683 : 0 : if (!asus_hides_ac97)
1684 : 0 : return;
1685 : :
1686 : 0 : pci_read_config_byte(dev, 0x50, &val);
1687 [ # # ]: 0 : if (val & 0xc0) {
1688 : 0 : pci_write_config_byte(dev, 0x50, val & (~0xc0));
1689 : 0 : pci_read_config_byte(dev, 0x50, &val);
1690 [ # # ]: 0 : if (val & 0xc0)
1691 : 0 : pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1692 : : val);
1693 : : else
1694 : 0 : pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1695 : : }
1696 : : }
1697 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1698 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1699 : :
1700 : : #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1701 : :
1702 : : /*
1703 : : * If we are using libata we can drive this chip properly but must do this
1704 : : * early on to make the additional device appear during the PCI scanning.
1705 : : */
1706 : 0 : static void quirk_jmicron_ata(struct pci_dev *pdev)
1707 : : {
1708 : 0 : u32 conf1, conf5, class;
1709 : 0 : u8 hdr;
1710 : :
1711 : : /* Only poke fn 0 */
1712 [ # # ]: 0 : if (PCI_FUNC(pdev->devfn))
1713 : 0 : return;
1714 : :
1715 : 0 : pci_read_config_dword(pdev, 0x40, &conf1);
1716 : 0 : pci_read_config_dword(pdev, 0x80, &conf5);
1717 : :
1718 : 0 : conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1719 : 0 : conf5 &= ~(1 << 24); /* Clear bit 24 */
1720 : :
1721 [ # # # # : 0 : switch (pdev->device) {
# ]
1722 : 0 : case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1723 : : case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1724 : : case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1725 : : /* The controller should be in single function ahci mode */
1726 : 0 : conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1727 : 0 : break;
1728 : :
1729 : 0 : case PCI_DEVICE_ID_JMICRON_JMB365:
1730 : : case PCI_DEVICE_ID_JMICRON_JMB366:
1731 : : /* Redirect IDE second PATA port to the right spot */
1732 : 0 : conf5 |= (1 << 24);
1733 : : /* Fall through */
1734 : 0 : case PCI_DEVICE_ID_JMICRON_JMB361:
1735 : : case PCI_DEVICE_ID_JMICRON_JMB363:
1736 : : case PCI_DEVICE_ID_JMICRON_JMB369:
1737 : : /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1738 : : /* Set the class codes correctly and then direct IDE 0 */
1739 : 0 : conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1740 : 0 : break;
1741 : :
1742 : 0 : case PCI_DEVICE_ID_JMICRON_JMB368:
1743 : : /* The controller should be in single function IDE mode */
1744 : 0 : conf1 |= 0x00C00000; /* Set 22, 23 */
1745 : 0 : break;
1746 : : }
1747 : :
1748 : 0 : pci_write_config_dword(pdev, 0x40, conf1);
1749 : 0 : pci_write_config_dword(pdev, 0x80, conf5);
1750 : :
1751 : : /* Update pdev accordingly */
1752 : 0 : pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1753 : 0 : pdev->hdr_type = hdr & 0x7f;
1754 : 0 : pdev->multifunction = !!(hdr & 0x80);
1755 : :
1756 : 0 : pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1757 : 0 : pdev->class = class >> 8;
1758 : : }
1759 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1760 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1761 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1762 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1763 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1764 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1765 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1766 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1767 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1768 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1769 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1770 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1771 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1772 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1773 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1774 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1775 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1776 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1777 : :
1778 : : #endif
1779 : :
1780 : 0 : static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1781 : : {
1782 [ # # ]: 0 : if (dev->multifunction) {
1783 [ # # ]: 0 : device_disable_async_suspend(&dev->dev);
1784 : 0 : pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1785 : : }
1786 : 0 : }
1787 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1788 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1789 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1790 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1791 : :
1792 : : #ifdef CONFIG_X86_IO_APIC
1793 : 0 : static void quirk_alder_ioapic(struct pci_dev *pdev)
1794 : : {
1795 : 0 : int i;
1796 : :
1797 [ # # ]: 0 : if ((pdev->class >> 8) != 0xff00)
1798 : : return;
1799 : :
1800 : : /*
1801 : : * The first BAR is the location of the IO-APIC... we must
1802 : : * not touch this (and it's already covered by the fixmap), so
1803 : : * forcibly insert it into the resource tree.
1804 : : */
1805 [ # # # # ]: 0 : if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1806 : 0 : insert_resource(&iomem_resource, &pdev->resource[0]);
1807 : :
1808 : : /*
1809 : : * The next five BARs all seem to be rubbish, so just clean
1810 : : * them out.
1811 : : */
1812 [ # # ]: 0 : for (i = 1; i < PCI_STD_NUM_BARS; i++)
1813 : 0 : memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1814 : : }
1815 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1816 : : #endif
1817 : :
1818 : 0 : static void quirk_pcie_mch(struct pci_dev *pdev)
1819 : : {
1820 : 0 : pdev->no_msi = 1;
1821 : 0 : }
1822 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1823 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1824 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1825 : :
1826 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1827 : :
1828 : : /*
1829 : : * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1830 : : * together on certain PXH-based systems.
1831 : : */
1832 : 0 : static void quirk_pcie_pxh(struct pci_dev *dev)
1833 : : {
1834 : 0 : dev->no_msi = 1;
1835 : 0 : pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1836 : 0 : }
1837 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1838 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1839 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1840 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1841 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1842 : :
1843 : : /*
1844 : : * Some Intel PCI Express chipsets have trouble with downstream device
1845 : : * power management.
1846 : : */
1847 : 0 : static void quirk_intel_pcie_pm(struct pci_dev *dev)
1848 : : {
1849 : 0 : pci_pm_d3_delay = 120;
1850 : 0 : dev->no_d1d2 = 1;
1851 : 0 : }
1852 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1853 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1854 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1855 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1856 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1857 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1858 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1859 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1860 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1861 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1862 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1863 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1864 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1865 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1866 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1867 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1868 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1869 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1870 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1871 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1872 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1873 : :
1874 : 0 : static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1875 : : {
1876 : 0 : if (dev->d3_delay >= delay)
1877 : : return;
1878 : :
1879 : 0 : dev->d3_delay = delay;
1880 : 0 : pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1881 : : dev->d3_delay);
1882 : : }
1883 : :
1884 : 0 : static void quirk_radeon_pm(struct pci_dev *dev)
1885 : : {
1886 [ # # ]: 0 : if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1887 : : dev->subsystem_device == 0x00e2)
1888 [ # # ]: 0 : quirk_d3hot_delay(dev, 20);
1889 : 0 : }
1890 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1891 : :
1892 : : /*
1893 : : * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1894 : : * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1895 : : *
1896 : : * The kernel attempts to transition these devices to D3cold, but that seems
1897 : : * to be ineffective on the platforms in question; the PCI device appears to
1898 : : * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1899 : : * extended delay in order to succeed.
1900 : : */
1901 : 0 : static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1902 : : {
1903 [ # # ]: 0 : quirk_d3hot_delay(dev, 20);
1904 : 0 : }
1905 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1906 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1907 : :
1908 : : #ifdef CONFIG_X86_IO_APIC
1909 : 0 : static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1910 : : {
1911 : 0 : noioapicreroute = 1;
1912 : 0 : pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1913 : :
1914 : 0 : return 0;
1915 : : }
1916 : :
1917 : : static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1918 : : /*
1919 : : * Systems to exclude from boot interrupt reroute quirks
1920 : : */
1921 : : {
1922 : : .callback = dmi_disable_ioapicreroute,
1923 : : .ident = "ASUSTek Computer INC. M2N-LR",
1924 : : .matches = {
1925 : : DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1926 : : DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1927 : : },
1928 : : },
1929 : : {}
1930 : : };
1931 : :
1932 : : /*
1933 : : * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1934 : : * remap the original interrupt in the Linux kernel to the boot interrupt, so
1935 : : * that a PCI device's interrupt handler is installed on the boot interrupt
1936 : : * line instead.
1937 : : */
1938 : 0 : static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1939 : : {
1940 : 0 : dmi_check_system(boot_interrupt_dmi_table);
1941 [ # # # # ]: 0 : if (noioapicquirk || noioapicreroute)
1942 : : return;
1943 : :
1944 : 0 : dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1945 : 0 : pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1946 : : dev->vendor, dev->device);
1947 : : }
1948 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1949 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1950 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1951 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1952 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1953 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1954 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1955 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1956 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1957 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1958 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1959 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1960 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1961 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1962 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1963 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1964 : :
1965 : : /*
1966 : : * On some chipsets we can disable the generation of legacy INTx boot
1967 : : * interrupts.
1968 : : */
1969 : :
1970 : : /*
1971 : : * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1972 : : * 300641-004US, section 5.7.3.
1973 : : */
1974 : : #define INTEL_6300_IOAPIC_ABAR 0x40
1975 : : #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1976 : :
1977 : 0 : static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1978 : : {
1979 : 0 : u16 pci_config_word;
1980 : :
1981 [ # # ]: 0 : if (noioapicquirk)
1982 : 0 : return;
1983 : :
1984 : 0 : pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1985 : 0 : pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1986 : 0 : pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1987 : :
1988 : 0 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1989 : : dev->vendor, dev->device);
1990 : : }
1991 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1992 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1993 : :
1994 : : /* Disable boot interrupts on HT-1000 */
1995 : : #define BC_HT1000_FEATURE_REG 0x64
1996 : : #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1997 : : #define BC_HT1000_MAP_IDX 0xC00
1998 : : #define BC_HT1000_MAP_DATA 0xC01
1999 : :
2000 : 0 : static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2001 : : {
2002 : 0 : u32 pci_config_dword;
2003 : 0 : u8 irq;
2004 : :
2005 [ # # ]: 0 : if (noioapicquirk)
2006 : 0 : return;
2007 : :
2008 : 0 : pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2009 : 0 : pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2010 : : BC_HT1000_PIC_REGS_ENABLE);
2011 : :
2012 [ # # ]: 0 : for (irq = 0x10; irq < 0x10 + 32; irq++) {
2013 : 0 : outb(irq, BC_HT1000_MAP_IDX);
2014 : 0 : outb(0x00, BC_HT1000_MAP_DATA);
2015 : : }
2016 : :
2017 : 0 : pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2018 : :
2019 : 0 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2020 : : dev->vendor, dev->device);
2021 : : }
2022 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2023 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2024 : :
2025 : : /* Disable boot interrupts on AMD and ATI chipsets */
2026 : :
2027 : : /*
2028 : : * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2029 : : * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2030 : : * (due to an erratum).
2031 : : */
2032 : : #define AMD_813X_MISC 0x40
2033 : : #define AMD_813X_NOIOAMODE (1<<0)
2034 : : #define AMD_813X_REV_B1 0x12
2035 : : #define AMD_813X_REV_B2 0x13
2036 : :
2037 : 0 : static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2038 : : {
2039 : 0 : u32 pci_config_dword;
2040 : :
2041 [ # # ]: 0 : if (noioapicquirk)
2042 : 0 : return;
2043 [ # # ]: 0 : if ((dev->revision == AMD_813X_REV_B1) ||
2044 : : (dev->revision == AMD_813X_REV_B2))
2045 : : return;
2046 : :
2047 : 0 : pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2048 : 0 : pci_config_dword &= ~AMD_813X_NOIOAMODE;
2049 : 0 : pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2050 : :
2051 : 0 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2052 : : dev->vendor, dev->device);
2053 : : }
2054 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2055 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2056 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2057 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2058 : :
2059 : : #define AMD_8111_PCI_IRQ_ROUTING 0x56
2060 : :
2061 : 0 : static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2062 : : {
2063 : 0 : u16 pci_config_word;
2064 : :
2065 [ # # ]: 0 : if (noioapicquirk)
2066 : 0 : return;
2067 : :
2068 : 0 : pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2069 [ # # ]: 0 : if (!pci_config_word) {
2070 : 0 : pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2071 : : dev->vendor, dev->device);
2072 : 0 : return;
2073 : : }
2074 : 0 : pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2075 : 0 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2076 : : dev->vendor, dev->device);
2077 : : }
2078 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2079 : : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2080 : : #endif /* CONFIG_X86_IO_APIC */
2081 : :
2082 : : /*
2083 : : * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2084 : : * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2085 : : * Re-allocate the region if needed...
2086 : : */
2087 : 0 : static void quirk_tc86c001_ide(struct pci_dev *dev)
2088 : : {
2089 : 0 : struct resource *r = &dev->resource[0];
2090 : :
2091 [ # # ]: 0 : if (r->start & 0x8) {
2092 : 0 : r->flags |= IORESOURCE_UNSET;
2093 : 0 : r->start = 0;
2094 : 0 : r->end = 0xf;
2095 : : }
2096 : 0 : }
2097 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2098 : : PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2099 : : quirk_tc86c001_ide);
2100 : :
2101 : : /*
2102 : : * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2103 : : * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2104 : : * being read correctly if bit 7 of the base address is set.
2105 : : * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2106 : : * Re-allocate the regions to a 256-byte boundary if necessary.
2107 : : */
2108 : 0 : static void quirk_plx_pci9050(struct pci_dev *dev)
2109 : : {
2110 : 0 : unsigned int bar;
2111 : :
2112 : : /* Fixed in revision 2 (PCI 9052). */
2113 [ # # ]: 0 : if (dev->revision >= 2)
2114 : : return;
2115 [ # # ]: 0 : for (bar = 0; bar <= 1; bar++)
2116 [ # # # # : 0 : if (pci_resource_len(dev, bar) == 0x80 &&
# # ]
2117 [ # # ]: 0 : (pci_resource_start(dev, bar) & 0x80)) {
2118 : 0 : struct resource *r = &dev->resource[bar];
2119 : 0 : pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2120 : : bar);
2121 : 0 : r->flags |= IORESOURCE_UNSET;
2122 : 0 : r->start = 0;
2123 : 0 : r->end = 0xff;
2124 : : }
2125 : : }
2126 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2127 : : quirk_plx_pci9050);
2128 : : /*
2129 : : * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2130 : : * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2131 : : * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2132 : : * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2133 : : *
2134 : : * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2135 : : * driver.
2136 : : */
2137 : : DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2138 : : DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2139 : :
2140 : 0 : static void quirk_netmos(struct pci_dev *dev)
2141 : : {
2142 : 0 : unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2143 : 0 : unsigned int num_serial = dev->subsystem_device & 0xf;
2144 : :
2145 : : /*
2146 : : * These Netmos parts are multiport serial devices with optional
2147 : : * parallel ports. Even when parallel ports are present, they
2148 : : * are identified as class SERIAL, which means the serial driver
2149 : : * will claim them. To prevent this, mark them as class OTHER.
2150 : : * These combo devices should be claimed by parport_serial.
2151 : : *
2152 : : * The subdevice ID is of the form 0x00PS, where <P> is the number
2153 : : * of parallel ports and <S> is the number of serial ports.
2154 : : */
2155 [ # # # ]: 0 : switch (dev->device) {
2156 : 0 : case PCI_DEVICE_ID_NETMOS_9835:
2157 : : /* Well, this rule doesn't hold for the following 9835 device */
2158 [ # # ]: 0 : if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2159 : : dev->subsystem_device == 0x0299)
2160 : : return;
2161 : : /* else, fall through */
2162 : : case PCI_DEVICE_ID_NETMOS_9735:
2163 : : case PCI_DEVICE_ID_NETMOS_9745:
2164 : : case PCI_DEVICE_ID_NETMOS_9845:
2165 : : case PCI_DEVICE_ID_NETMOS_9855:
2166 [ # # ]: 0 : if (num_parallel) {
2167 : 0 : pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2168 : : dev->device, num_parallel, num_serial);
2169 : 0 : dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2170 : 0 : (dev->class & 0xff);
2171 : : }
2172 : : }
2173 : : }
2174 : : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2175 : : PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2176 : :
2177 : 0 : static void quirk_e100_interrupt(struct pci_dev *dev)
2178 : : {
2179 : 0 : u16 command, pmcsr;
2180 : 0 : u8 __iomem *csr;
2181 : 0 : u8 cmd_hi;
2182 : :
2183 [ # # ]: 0 : switch (dev->device) {
2184 : : /* PCI IDs taken from drivers/net/e100.c */
2185 : : case 0x1029:
2186 : : case 0x1030 ... 0x1034:
2187 : : case 0x1038 ... 0x103E:
2188 : : case 0x1050 ... 0x1057:
2189 : : case 0x1059:
2190 : : case 0x1064 ... 0x106B:
2191 : : case 0x1091 ... 0x1095:
2192 : : case 0x1209:
2193 : : case 0x1229:
2194 : : case 0x2449:
2195 : : case 0x2459:
2196 : : case 0x245D:
2197 : : case 0x27DC:
2198 : 0 : break;
2199 : : default:
2200 : 0 : return;
2201 : : }
2202 : :
2203 : : /*
2204 : : * Some firmware hands off the e100 with interrupts enabled,
2205 : : * which can cause a flood of interrupts if packets are
2206 : : * received before the driver attaches to the device. So
2207 : : * disable all e100 interrupts here. The driver will
2208 : : * re-enable them when it's ready.
2209 : : */
2210 : 0 : pci_read_config_word(dev, PCI_COMMAND, &command);
2211 : :
2212 [ # # # # ]: 0 : if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2213 : : return;
2214 : :
2215 : : /*
2216 : : * Check that the device is in the D0 power state. If it's not,
2217 : : * there is no point to look any further.
2218 : : */
2219 [ # # ]: 0 : if (dev->pm_cap) {
2220 : 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2221 [ # # ]: 0 : if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2222 : : return;
2223 : : }
2224 : :
2225 : : /* Convert from PCI bus to resource space. */
2226 : 0 : csr = ioremap(pci_resource_start(dev, 0), 8);
2227 [ # # ]: 0 : if (!csr) {
2228 : 0 : pci_warn(dev, "Can't map e100 registers\n");
2229 : 0 : return;
2230 : : }
2231 : :
2232 : 0 : cmd_hi = readb(csr + 3);
2233 [ # # ]: 0 : if (cmd_hi == 0) {
2234 : 0 : pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2235 : 0 : writeb(1, csr + 3);
2236 : : }
2237 : :
2238 : 0 : iounmap(csr);
2239 : : }
2240 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2241 : : PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2242 : :
2243 : : /*
2244 : : * The 82575 and 82598 may experience data corruption issues when transitioning
2245 : : * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2246 : : */
2247 : 0 : static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2248 : : {
2249 : 0 : pci_info(dev, "Disabling L0s\n");
2250 : 0 : pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2251 : 0 : }
2252 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2253 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2254 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2255 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2256 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2257 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2258 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2259 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2260 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2261 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2262 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2263 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2264 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2265 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2266 : :
2267 : : /*
2268 : : * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2269 : : * Link bit cleared after starting the link retrain process to allow this
2270 : : * process to finish.
2271 : : *
2272 : : * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2273 : : * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2274 : : */
2275 : 0 : static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2276 : : {
2277 : 0 : dev->clear_retrain_link = 1;
2278 : 0 : pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2279 : 0 : }
2280 : : DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2281 : : DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2282 : : DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2283 : :
2284 : 0 : static void fixup_rev1_53c810(struct pci_dev *dev)
2285 : : {
2286 : 0 : u32 class = dev->class;
2287 : :
2288 : : /*
2289 : : * rev 1 ncr53c810 chips don't set the class at all which means
2290 : : * they don't get their resources remapped. Fix that here.
2291 : : */
2292 [ # # ]: 0 : if (class)
2293 : : return;
2294 : :
2295 : 0 : dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2296 : 0 : pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2297 : : class, dev->class);
2298 : : }
2299 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2300 : :
2301 : : /* Enable 1k I/O space granularity on the Intel P64H2 */
2302 : 0 : static void quirk_p64h2_1k_io(struct pci_dev *dev)
2303 : : {
2304 : 0 : u16 en1k;
2305 : :
2306 : 0 : pci_read_config_word(dev, 0x40, &en1k);
2307 : :
2308 [ # # ]: 0 : if (en1k & 0x200) {
2309 : 0 : pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2310 : 0 : dev->io_window_1k = 1;
2311 : : }
2312 : 0 : }
2313 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2314 : :
2315 : : /*
2316 : : * Under some circumstances, AER is not linked with extended capabilities.
2317 : : * Force it to be linked by setting the corresponding control bit in the
2318 : : * config space.
2319 : : */
2320 : 0 : static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2321 : : {
2322 : 0 : uint8_t b;
2323 : :
2324 [ # # ]: 0 : if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2325 [ # # ]: 0 : if (!(b & 0x20)) {
2326 : 0 : pci_write_config_byte(dev, 0xf41, b | 0x20);
2327 : 0 : pci_info(dev, "Linking AER extended capability\n");
2328 : : }
2329 : : }
2330 : 0 : }
2331 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2332 : : quirk_nvidia_ck804_pcie_aer_ext_cap);
2333 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2334 : : quirk_nvidia_ck804_pcie_aer_ext_cap);
2335 : :
2336 : 0 : static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2337 : : {
2338 : : /*
2339 : : * Disable PCI Bus Parking and PCI Master read caching on CX700
2340 : : * which causes unspecified timing errors with a VT6212L on the PCI
2341 : : * bus leading to USB2.0 packet loss.
2342 : : *
2343 : : * This quirk is only enabled if a second (on the external PCI bus)
2344 : : * VT6212L is found -- the CX700 core itself also contains a USB
2345 : : * host controller with the same PCI ID as the VT6212L.
2346 : : */
2347 : :
2348 : : /* Count VT6212L instances */
2349 : 0 : struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2350 : : PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2351 : 0 : uint8_t b;
2352 : :
2353 : : /*
2354 : : * p should contain the first (internal) VT6212L -- see if we have
2355 : : * an external one by searching again.
2356 : : */
2357 : 0 : p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2358 [ # # ]: 0 : if (!p)
2359 : 0 : return;
2360 : 0 : pci_dev_put(p);
2361 : :
2362 [ # # ]: 0 : if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2363 [ # # ]: 0 : if (b & 0x40) {
2364 : : /* Turn off PCI Bus Parking */
2365 : 0 : pci_write_config_byte(dev, 0x76, b ^ 0x40);
2366 : :
2367 : 0 : pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2368 : : }
2369 : : }
2370 : :
2371 [ # # ]: 0 : if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2372 [ # # ]: 0 : if (b != 0) {
2373 : : /* Turn off PCI Master read caching */
2374 : 0 : pci_write_config_byte(dev, 0x72, 0x0);
2375 : :
2376 : : /* Set PCI Master Bus time-out to "1x16 PCLK" */
2377 : 0 : pci_write_config_byte(dev, 0x75, 0x1);
2378 : :
2379 : : /* Disable "Read FIFO Timer" */
2380 : 0 : pci_write_config_byte(dev, 0x77, 0x0);
2381 : :
2382 : 0 : pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2383 : : }
2384 : : }
2385 : : }
2386 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2387 : :
2388 : 0 : static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2389 : : {
2390 : 0 : u32 rev;
2391 : :
2392 : 0 : pci_read_config_dword(dev, 0xf4, &rev);
2393 : :
2394 : : /* Only CAP the MRRS if the device is a 5719 A0 */
2395 [ # # ]: 0 : if (rev == 0x05719000) {
2396 : 0 : int readrq = pcie_get_readrq(dev);
2397 [ # # ]: 0 : if (readrq > 2048)
2398 : 0 : pcie_set_readrq(dev, 2048);
2399 : : }
2400 : 0 : }
2401 : : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2402 : : PCI_DEVICE_ID_TIGON3_5719,
2403 : : quirk_brcm_5719_limit_mrrs);
2404 : :
2405 : : /*
2406 : : * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2407 : : * hide device 6 which configures the overflow device access containing the
2408 : : * DRBs - this is where we expose device 6.
2409 : : * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2410 : : */
2411 : 0 : static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2412 : : {
2413 : 0 : u8 reg;
2414 : :
2415 [ # # # # ]: 0 : if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2416 : 0 : pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2417 : 0 : pci_write_config_byte(dev, 0xF4, reg | 0x02);
2418 : : }
2419 : 0 : }
2420 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2421 : : quirk_unhide_mch_dev6);
2422 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2423 : : quirk_unhide_mch_dev6);
2424 : :
2425 : : #ifdef CONFIG_PCI_MSI
2426 : : /*
2427 : : * Some chipsets do not support MSI. We cannot easily rely on setting
2428 : : * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2429 : : * other buses controlled by the chipset even if Linux is not aware of it.
2430 : : * Instead of setting the flag on all buses in the machine, simply disable
2431 : : * MSI globally.
2432 : : */
2433 : 0 : static void quirk_disable_all_msi(struct pci_dev *dev)
2434 : : {
2435 : 0 : pci_no_msi();
2436 : 0 : pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2437 : 0 : }
2438 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2439 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2440 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2441 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2442 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2443 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2444 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2445 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2446 : :
2447 : : /* Disable MSI on chipsets that are known to not support it */
2448 : 0 : static void quirk_disable_msi(struct pci_dev *dev)
2449 : : {
2450 [ # # ]: 0 : if (dev->subordinate) {
2451 : 0 : pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2452 : 0 : dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2453 : : }
2454 : 0 : }
2455 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2456 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2457 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2458 : :
2459 : : /*
2460 : : * The APC bridge device in AMD 780 family northbridges has some random
2461 : : * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2462 : : * we use the possible vendor/device IDs of the host bridge for the
2463 : : * declared quirk, and search for the APC bridge by slot number.
2464 : : */
2465 : 0 : static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2466 : : {
2467 : 0 : struct pci_dev *apc_bridge;
2468 : :
2469 : 0 : apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2470 [ # # ]: 0 : if (apc_bridge) {
2471 [ # # ]: 0 : if (apc_bridge->device == 0x9602)
2472 [ # # ]: 0 : quirk_disable_msi(apc_bridge);
2473 : 0 : pci_dev_put(apc_bridge);
2474 : : }
2475 : 0 : }
2476 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2477 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2478 : :
2479 : : /*
2480 : : * Go through the list of HyperTransport capabilities and return 1 if a HT
2481 : : * MSI capability is found and enabled.
2482 : : */
2483 : 0 : static int msi_ht_cap_enabled(struct pci_dev *dev)
2484 : : {
2485 : 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2486 : :
2487 : 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2488 [ # # # # ]: 0 : while (pos && ttl--) {
2489 : 0 : u8 flags;
2490 : :
2491 [ # # ]: 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2492 : : &flags) == 0) {
2493 [ # # ]: 0 : pci_info(dev, "Found %s HT MSI Mapping\n",
2494 : : flags & HT_MSI_FLAGS_ENABLE ?
2495 : : "enabled" : "disabled");
2496 : 0 : return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2497 : : }
2498 : :
2499 : 0 : pos = pci_find_next_ht_capability(dev, pos,
2500 : : HT_CAPTYPE_MSI_MAPPING);
2501 : : }
2502 : : return 0;
2503 : : }
2504 : :
2505 : : /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2506 : 0 : static void quirk_msi_ht_cap(struct pci_dev *dev)
2507 : : {
2508 [ # # # # ]: 0 : if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2509 : 0 : pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2510 : 0 : dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2511 : : }
2512 : 0 : }
2513 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2514 : : quirk_msi_ht_cap);
2515 : :
2516 : : /*
2517 : : * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2518 : : * if the MSI capability is set in any of these mappings.
2519 : : */
2520 : 0 : static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2521 : : {
2522 : 0 : struct pci_dev *pdev;
2523 : :
2524 [ # # ]: 0 : if (!dev->subordinate)
2525 : : return;
2526 : :
2527 : : /*
2528 : : * Check HT MSI cap on this chipset and the root one. A single one
2529 : : * having MSI is enough to be sure that MSI is supported.
2530 : : */
2531 : 0 : pdev = pci_get_slot(dev->bus, 0);
2532 [ # # ]: 0 : if (!pdev)
2533 : : return;
2534 [ # # # # ]: 0 : if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2535 : 0 : pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2536 : 0 : dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2537 : : }
2538 : 0 : pci_dev_put(pdev);
2539 : : }
2540 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2541 : : quirk_nvidia_ck804_msi_ht_cap);
2542 : :
2543 : : /* Force enable MSI mapping capability on HT bridges */
2544 : 0 : static void ht_enable_msi_mapping(struct pci_dev *dev)
2545 : : {
2546 : 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2547 : :
2548 : 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2549 [ # # # # ]: 0 : while (pos && ttl--) {
2550 : 0 : u8 flags;
2551 : :
2552 [ # # ]: 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2553 : : &flags) == 0) {
2554 : 0 : pci_info(dev, "Enabling HT MSI Mapping\n");
2555 : :
2556 : 0 : pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2557 : : flags | HT_MSI_FLAGS_ENABLE);
2558 : : }
2559 : 0 : pos = pci_find_next_ht_capability(dev, pos,
2560 : : HT_CAPTYPE_MSI_MAPPING);
2561 : : }
2562 : 0 : }
2563 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2564 : : PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2565 : : ht_enable_msi_mapping);
2566 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2567 : : ht_enable_msi_mapping);
2568 : :
2569 : : /*
2570 : : * The P5N32-SLI motherboards from Asus have a problem with MSI
2571 : : * for the MCP55 NIC. It is not yet determined whether the MSI problem
2572 : : * also affects other devices. As for now, turn off MSI for this device.
2573 : : */
2574 : 0 : static void nvenet_msi_disable(struct pci_dev *dev)
2575 : : {
2576 : 0 : const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2577 : :
2578 [ # # ]: 0 : if (board_name &&
2579 [ # # ]: 0 : (strstr(board_name, "P5N32-SLI PREMIUM") ||
2580 [ # # ]: 0 : strstr(board_name, "P5N32-E SLI"))) {
2581 : 0 : pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2582 : 0 : dev->no_msi = 1;
2583 : : }
2584 : 0 : }
2585 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2586 : : PCI_DEVICE_ID_NVIDIA_NVENET_15,
2587 : : nvenet_msi_disable);
2588 : :
2589 : : /*
2590 : : * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2591 : : * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2592 : : * generate MSI interrupts for PME and AER events instead only INTx interrupts
2593 : : * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2594 : : * for other events, since PCIe specificiation doesn't support using a mix of
2595 : : * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2596 : : * service drivers registering their respective ISRs for MSIs.
2597 : : */
2598 : 0 : static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2599 : : {
2600 : 0 : dev->no_msi = 1;
2601 : 0 : }
2602 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2603 : : PCI_CLASS_BRIDGE_PCI, 8,
2604 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2605 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2606 : : PCI_CLASS_BRIDGE_PCI, 8,
2607 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2608 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2609 : : PCI_CLASS_BRIDGE_PCI, 8,
2610 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2611 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2612 : : PCI_CLASS_BRIDGE_PCI, 8,
2613 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2614 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2615 : : PCI_CLASS_BRIDGE_PCI, 8,
2616 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2617 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2618 : : PCI_CLASS_BRIDGE_PCI, 8,
2619 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2620 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2621 : : PCI_CLASS_BRIDGE_PCI, 8,
2622 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2623 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2624 : : PCI_CLASS_BRIDGE_PCI, 8,
2625 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2626 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2627 : : PCI_CLASS_BRIDGE_PCI, 8,
2628 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2629 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2630 : : PCI_CLASS_BRIDGE_PCI, 8,
2631 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2632 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2633 : : PCI_CLASS_BRIDGE_PCI, 8,
2634 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2635 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2636 : : PCI_CLASS_BRIDGE_PCI, 8,
2637 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2638 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2639 : : PCI_CLASS_BRIDGE_PCI, 8,
2640 : : pci_quirk_nvidia_tegra_disable_rp_msi);
2641 : :
2642 : : /*
2643 : : * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2644 : : * config register. This register controls the routing of legacy
2645 : : * interrupts from devices that route through the MCP55. If this register
2646 : : * is misprogrammed, interrupts are only sent to the BSP, unlike
2647 : : * conventional systems where the IRQ is broadcast to all online CPUs. Not
2648 : : * having this register set properly prevents kdump from booting up
2649 : : * properly, so let's make sure that we have it set correctly.
2650 : : * Note that this is an undocumented register.
2651 : : */
2652 : 0 : static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2653 : : {
2654 : 0 : u32 cfg;
2655 : :
2656 [ # # ]: 0 : if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2657 : 0 : return;
2658 : :
2659 : 0 : pci_read_config_dword(dev, 0x74, &cfg);
2660 : :
2661 [ # # ]: 0 : if (cfg & ((1 << 2) | (1 << 15))) {
2662 : 0 : pr_info("Rewriting IRQ routing register on MCP55\n");
2663 : 0 : cfg &= ~((1 << 2) | (1 << 15));
2664 : 0 : pci_write_config_dword(dev, 0x74, cfg);
2665 : : }
2666 : : }
2667 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2668 : : PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2669 : : nvbridge_check_legacy_irq_routing);
2670 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2671 : : PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2672 : : nvbridge_check_legacy_irq_routing);
2673 : :
2674 : 0 : static int ht_check_msi_mapping(struct pci_dev *dev)
2675 : : {
2676 : 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2677 : 0 : int found = 0;
2678 : :
2679 : : /* Check if there is HT MSI cap or enabled on this device */
2680 : 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2681 [ # # # # ]: 0 : while (pos && ttl--) {
2682 : 0 : u8 flags;
2683 : :
2684 : 0 : if (found < 1)
2685 : : found = 1;
2686 [ # # ]: 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2687 : : &flags) == 0) {
2688 [ # # ]: 0 : if (flags & HT_MSI_FLAGS_ENABLE) {
2689 [ # # ]: 0 : if (found < 2) {
2690 : 0 : found = 2;
2691 : 0 : break;
2692 : : }
2693 : : }
2694 : : }
2695 : 0 : pos = pci_find_next_ht_capability(dev, pos,
2696 : : HT_CAPTYPE_MSI_MAPPING);
2697 : : }
2698 : :
2699 : 0 : return found;
2700 : : }
2701 : :
2702 : : static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2703 : : {
2704 : : struct pci_dev *dev;
2705 : : int pos;
2706 : : int i, dev_no;
2707 : : int found = 0;
2708 : :
2709 : : dev_no = host_bridge->devfn >> 3;
2710 : : for (i = dev_no + 1; i < 0x20; i++) {
2711 : : dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2712 : : if (!dev)
2713 : : continue;
2714 : :
2715 : : /* found next host bridge? */
2716 : : pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2717 : : if (pos != 0) {
2718 : : pci_dev_put(dev);
2719 : : break;
2720 : : }
2721 : :
2722 : : if (ht_check_msi_mapping(dev)) {
2723 : : found = 1;
2724 : : pci_dev_put(dev);
2725 : : break;
2726 : : }
2727 : : pci_dev_put(dev);
2728 : : }
2729 : :
2730 : : return found;
2731 : : }
2732 : :
2733 : : #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2734 : : #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2735 : :
2736 : 0 : static int is_end_of_ht_chain(struct pci_dev *dev)
2737 : : {
2738 : 0 : int pos, ctrl_off;
2739 : 0 : int end = 0;
2740 : 0 : u16 flags, ctrl;
2741 : :
2742 : 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2743 : :
2744 [ # # ]: 0 : if (!pos)
2745 : 0 : goto out;
2746 : :
2747 : 0 : pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2748 : :
2749 : 0 : ctrl_off = ((flags >> 10) & 1) ?
2750 [ # # ]: 0 : PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2751 : 0 : pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2752 : :
2753 [ # # ]: 0 : if (ctrl & (1 << 6))
2754 : 0 : end = 1;
2755 : :
2756 : 0 : out:
2757 : 0 : return end;
2758 : : }
2759 : :
2760 : 0 : static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2761 : : {
2762 : 0 : struct pci_dev *host_bridge;
2763 : 0 : int pos;
2764 : 0 : int i, dev_no;
2765 : 0 : int found = 0;
2766 : :
2767 : 0 : dev_no = dev->devfn >> 3;
2768 [ # # ]: 0 : for (i = dev_no; i >= 0; i--) {
2769 : 0 : host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2770 [ # # ]: 0 : if (!host_bridge)
2771 : 0 : continue;
2772 : :
2773 : 0 : pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2774 [ # # ]: 0 : if (pos != 0) {
2775 : : found = 1;
2776 : : break;
2777 : : }
2778 : 0 : pci_dev_put(host_bridge);
2779 : : }
2780 : :
2781 [ # # ]: 0 : if (!found)
2782 : : return;
2783 : :
2784 : : /* don't enable end_device/host_bridge with leaf directly here */
2785 [ # # # # : 0 : if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
# # ]
2786 : 0 : host_bridge_with_leaf(host_bridge))
2787 : 0 : goto out;
2788 : :
2789 : : /* root did that ! */
2790 [ # # ]: 0 : if (msi_ht_cap_enabled(host_bridge))
2791 : 0 : goto out;
2792 : :
2793 : 0 : ht_enable_msi_mapping(dev);
2794 : :
2795 : 0 : out:
2796 : 0 : pci_dev_put(host_bridge);
2797 : : }
2798 : :
2799 : 0 : static void ht_disable_msi_mapping(struct pci_dev *dev)
2800 : : {
2801 : 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2802 : :
2803 : 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2804 [ # # # # ]: 0 : while (pos && ttl--) {
2805 : 0 : u8 flags;
2806 : :
2807 [ # # ]: 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2808 : : &flags) == 0) {
2809 : 0 : pci_info(dev, "Disabling HT MSI Mapping\n");
2810 : :
2811 : 0 : pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2812 : 0 : flags & ~HT_MSI_FLAGS_ENABLE);
2813 : : }
2814 : 0 : pos = pci_find_next_ht_capability(dev, pos,
2815 : : HT_CAPTYPE_MSI_MAPPING);
2816 : : }
2817 : 0 : }
2818 : :
2819 : 0 : static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2820 : : {
2821 : 0 : struct pci_dev *host_bridge;
2822 : 0 : int pos;
2823 : 0 : int found;
2824 : :
2825 [ # # ]: 0 : if (!pci_msi_enabled())
2826 : : return;
2827 : :
2828 : : /* check if there is HT MSI cap or enabled on this device */
2829 : 0 : found = ht_check_msi_mapping(dev);
2830 : :
2831 : : /* no HT MSI CAP */
2832 [ # # ]: 0 : if (found == 0)
2833 : : return;
2834 : :
2835 : : /*
2836 : : * HT MSI mapping should be disabled on devices that are below
2837 : : * a non-Hypertransport host bridge. Locate the host bridge...
2838 : : */
2839 : 0 : host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2840 : : PCI_DEVFN(0, 0));
2841 [ # # ]: 0 : if (host_bridge == NULL) {
2842 : 0 : pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2843 : 0 : return;
2844 : : }
2845 : :
2846 : 0 : pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2847 [ # # ]: 0 : if (pos != 0) {
2848 : : /* Host bridge is to HT */
2849 [ # # ]: 0 : if (found == 1) {
2850 : : /* it is not enabled, try to enable it */
2851 [ # # ]: 0 : if (all)
2852 : 0 : ht_enable_msi_mapping(dev);
2853 : : else
2854 : 0 : nv_ht_enable_msi_mapping(dev);
2855 : : }
2856 : 0 : goto out;
2857 : : }
2858 : :
2859 : : /* HT MSI is not enabled */
2860 [ # # ]: 0 : if (found == 1)
2861 : 0 : goto out;
2862 : :
2863 : : /* Host bridge is not to HT, disable HT MSI mapping on this device */
2864 : 0 : ht_disable_msi_mapping(dev);
2865 : :
2866 : 0 : out:
2867 : 0 : pci_dev_put(host_bridge);
2868 : : }
2869 : :
2870 : 0 : static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2871 : : {
2872 : 0 : return __nv_msi_ht_cap_quirk(dev, 1);
2873 : : }
2874 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2875 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2876 : :
2877 : 0 : static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2878 : : {
2879 : 0 : return __nv_msi_ht_cap_quirk(dev, 0);
2880 : : }
2881 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2882 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2883 : :
2884 : 0 : static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2885 : : {
2886 : 0 : dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2887 : 0 : }
2888 : :
2889 : 0 : static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2890 : : {
2891 : 0 : struct pci_dev *p;
2892 : :
2893 : : /*
2894 : : * SB700 MSI issue will be fixed at HW level from revision A21;
2895 : : * we need check PCI REVISION ID of SMBus controller to get SB700
2896 : : * revision.
2897 : : */
2898 : 0 : p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2899 : : NULL);
2900 [ # # ]: 0 : if (!p)
2901 : : return;
2902 : :
2903 [ # # ]: 0 : if ((p->revision < 0x3B) && (p->revision >= 0x30))
2904 : 0 : dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2905 : 0 : pci_dev_put(p);
2906 : : }
2907 : :
2908 : 0 : static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2909 : : {
2910 : : /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2911 [ # # ]: 0 : if (dev->revision < 0x18) {
2912 : 0 : pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2913 : 0 : dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2914 : : }
2915 : 0 : }
2916 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2917 : : PCI_DEVICE_ID_TIGON3_5780,
2918 : : quirk_msi_intx_disable_bug);
2919 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2920 : : PCI_DEVICE_ID_TIGON3_5780S,
2921 : : quirk_msi_intx_disable_bug);
2922 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2923 : : PCI_DEVICE_ID_TIGON3_5714,
2924 : : quirk_msi_intx_disable_bug);
2925 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2926 : : PCI_DEVICE_ID_TIGON3_5714S,
2927 : : quirk_msi_intx_disable_bug);
2928 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2929 : : PCI_DEVICE_ID_TIGON3_5715,
2930 : : quirk_msi_intx_disable_bug);
2931 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2932 : : PCI_DEVICE_ID_TIGON3_5715S,
2933 : : quirk_msi_intx_disable_bug);
2934 : :
2935 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2936 : : quirk_msi_intx_disable_ati_bug);
2937 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2938 : : quirk_msi_intx_disable_ati_bug);
2939 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2940 : : quirk_msi_intx_disable_ati_bug);
2941 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2942 : : quirk_msi_intx_disable_ati_bug);
2943 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2944 : : quirk_msi_intx_disable_ati_bug);
2945 : :
2946 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2947 : : quirk_msi_intx_disable_bug);
2948 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2949 : : quirk_msi_intx_disable_bug);
2950 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2951 : : quirk_msi_intx_disable_bug);
2952 : :
2953 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2954 : : quirk_msi_intx_disable_bug);
2955 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2956 : : quirk_msi_intx_disable_bug);
2957 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2958 : : quirk_msi_intx_disable_bug);
2959 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2960 : : quirk_msi_intx_disable_bug);
2961 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2962 : : quirk_msi_intx_disable_bug);
2963 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2964 : : quirk_msi_intx_disable_bug);
2965 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2966 : : quirk_msi_intx_disable_qca_bug);
2967 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2968 : : quirk_msi_intx_disable_qca_bug);
2969 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2970 : : quirk_msi_intx_disable_qca_bug);
2971 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2972 : : quirk_msi_intx_disable_qca_bug);
2973 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2974 : : quirk_msi_intx_disable_qca_bug);
2975 : :
2976 : : /*
2977 : : * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
2978 : : * should be disabled on platforms where the device (mistakenly) advertises it.
2979 : : *
2980 : : * Notice that this quirk also disables MSI (which may work, but hasn't been
2981 : : * tested), since currently there is no standard way to disable only MSI-X.
2982 : : *
2983 : : * The 0031 device id is reused for other non Root Port device types,
2984 : : * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
2985 : : */
2986 : 0 : static void quirk_al_msi_disable(struct pci_dev *dev)
2987 : : {
2988 : 0 : dev->no_msi = 1;
2989 : 0 : pci_warn(dev, "Disabling MSI/MSI-X\n");
2990 : 0 : }
2991 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
2992 : : PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
2993 : : #endif /* CONFIG_PCI_MSI */
2994 : :
2995 : : /*
2996 : : * Allow manual resource allocation for PCI hotplug bridges via
2997 : : * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
2998 : : * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
2999 : : * allocate resources when hotplug device is inserted and PCI bus is
3000 : : * rescanned.
3001 : : */
3002 : 0 : static void quirk_hotplug_bridge(struct pci_dev *dev)
3003 : : {
3004 : 0 : dev->is_hotplug_bridge = 1;
3005 : 0 : }
3006 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3007 : :
3008 : : /*
3009 : : * This is a quirk for the Ricoh MMC controller found as a part of some
3010 : : * multifunction chips.
3011 : : *
3012 : : * This is very similar and based on the ricoh_mmc driver written by
3013 : : * Philip Langdale. Thank you for these magic sequences.
3014 : : *
3015 : : * These chips implement the four main memory card controllers (SD, MMC,
3016 : : * MS, xD) and one or both of CardBus or FireWire.
3017 : : *
3018 : : * It happens that they implement SD and MMC support as separate
3019 : : * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3020 : : * cards but the chip detects MMC cards in hardware and directs them to the
3021 : : * MMC controller - so the SDHCI driver never sees them.
3022 : : *
3023 : : * To get around this, we must disable the useless MMC controller. At that
3024 : : * point, the SDHCI controller will start seeing them. It seems to be the
3025 : : * case that the relevant PCI registers to deactivate the MMC controller
3026 : : * live on PCI function 0, which might be the CardBus controller or the
3027 : : * FireWire controller, depending on the particular chip in question
3028 : : *
3029 : : * This has to be done early, because as soon as we disable the MMC controller
3030 : : * other PCI functions shift up one level, e.g. function #2 becomes function
3031 : : * #1, and this will confuse the PCI core.
3032 : : */
3033 : : #ifdef CONFIG_MMC_RICOH_MMC
3034 : : static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3035 : : {
3036 : : u8 write_enable;
3037 : : u8 write_target;
3038 : : u8 disable;
3039 : :
3040 : : /*
3041 : : * Disable via CardBus interface
3042 : : *
3043 : : * This must be done via function #0
3044 : : */
3045 : : if (PCI_FUNC(dev->devfn))
3046 : : return;
3047 : :
3048 : : pci_read_config_byte(dev, 0xB7, &disable);
3049 : : if (disable & 0x02)
3050 : : return;
3051 : :
3052 : : pci_read_config_byte(dev, 0x8E, &write_enable);
3053 : : pci_write_config_byte(dev, 0x8E, 0xAA);
3054 : : pci_read_config_byte(dev, 0x8D, &write_target);
3055 : : pci_write_config_byte(dev, 0x8D, 0xB7);
3056 : : pci_write_config_byte(dev, 0xB7, disable | 0x02);
3057 : : pci_write_config_byte(dev, 0x8E, write_enable);
3058 : : pci_write_config_byte(dev, 0x8D, write_target);
3059 : :
3060 : : pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3061 : : pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3062 : : }
3063 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3064 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3065 : :
3066 : : static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3067 : : {
3068 : : u8 write_enable;
3069 : : u8 disable;
3070 : :
3071 : : /*
3072 : : * Disable via FireWire interface
3073 : : *
3074 : : * This must be done via function #0
3075 : : */
3076 : : if (PCI_FUNC(dev->devfn))
3077 : : return;
3078 : : /*
3079 : : * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3080 : : * certain types of SD/MMC cards. Lowering the SD base clock
3081 : : * frequency from 200Mhz to 50Mhz fixes this issue.
3082 : : *
3083 : : * 0x150 - SD2.0 mode enable for changing base clock
3084 : : * frequency to 50Mhz
3085 : : * 0xe1 - Base clock frequency
3086 : : * 0x32 - 50Mhz new clock frequency
3087 : : * 0xf9 - Key register for 0x150
3088 : : * 0xfc - key register for 0xe1
3089 : : */
3090 : : if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3091 : : dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3092 : : pci_write_config_byte(dev, 0xf9, 0xfc);
3093 : : pci_write_config_byte(dev, 0x150, 0x10);
3094 : : pci_write_config_byte(dev, 0xf9, 0x00);
3095 : : pci_write_config_byte(dev, 0xfc, 0x01);
3096 : : pci_write_config_byte(dev, 0xe1, 0x32);
3097 : : pci_write_config_byte(dev, 0xfc, 0x00);
3098 : :
3099 : : pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3100 : : }
3101 : :
3102 : : pci_read_config_byte(dev, 0xCB, &disable);
3103 : :
3104 : : if (disable & 0x02)
3105 : : return;
3106 : :
3107 : : pci_read_config_byte(dev, 0xCA, &write_enable);
3108 : : pci_write_config_byte(dev, 0xCA, 0x57);
3109 : : pci_write_config_byte(dev, 0xCB, disable | 0x02);
3110 : : pci_write_config_byte(dev, 0xCA, write_enable);
3111 : :
3112 : : pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3113 : : pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3114 : :
3115 : : }
3116 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3117 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3118 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3119 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3120 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3121 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3122 : : #endif /*CONFIG_MMC_RICOH_MMC*/
3123 : :
3124 : : #ifdef CONFIG_DMAR_TABLE
3125 : : #define VTUNCERRMSK_REG 0x1ac
3126 : : #define VTD_MSK_SPEC_ERRORS (1 << 31)
3127 : : /*
3128 : : * This is a quirk for masking VT-d spec-defined errors to platform error
3129 : : * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3130 : : * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3131 : : * on the RAS config settings of the platform) when a VT-d fault happens.
3132 : : * The resulting SMI caused the system to hang.
3133 : : *
3134 : : * VT-d spec-related errors are already handled by the VT-d OS code, so no
3135 : : * need to report the same error through other channels.
3136 : : */
3137 : 0 : static void vtd_mask_spec_errors(struct pci_dev *dev)
3138 : : {
3139 : 0 : u32 word;
3140 : :
3141 : 0 : pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3142 : 0 : pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3143 : 0 : }
3144 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3145 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3146 : : #endif
3147 : :
3148 : 0 : static void fixup_ti816x_class(struct pci_dev *dev)
3149 : : {
3150 : 0 : u32 class = dev->class;
3151 : :
3152 : : /* TI 816x devices do not have class code set when in PCIe boot mode */
3153 : 0 : dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3154 : 0 : pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3155 : : class, dev->class);
3156 : 0 : }
3157 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3158 : : PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3159 : :
3160 : : /*
3161 : : * Some PCIe devices do not work reliably with the claimed maximum
3162 : : * payload size supported.
3163 : : */
3164 : 0 : static void fixup_mpss_256(struct pci_dev *dev)
3165 : : {
3166 : 0 : dev->pcie_mpss = 1; /* 256 bytes */
3167 : 0 : }
3168 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3169 : : PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3170 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3171 : : PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3172 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3173 : : PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3174 : :
3175 : : /*
3176 : : * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3177 : : * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3178 : : * Since there is no way of knowing what the PCIe MPS on each fabric will be
3179 : : * until all of the devices are discovered and buses walked, read completion
3180 : : * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3181 : : * it is possible to hotplug a device with MPS of 256B.
3182 : : */
3183 : 0 : static void quirk_intel_mc_errata(struct pci_dev *dev)
3184 : : {
3185 : 0 : int err;
3186 : 0 : u16 rcc;
3187 : :
3188 [ # # ]: 0 : if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3189 : : pcie_bus_config == PCIE_BUS_DEFAULT)
3190 : 0 : return;
3191 : :
3192 : : /*
3193 : : * Intel erratum specifies bits to change but does not say what
3194 : : * they are. Keeping them magical until such time as the registers
3195 : : * and values can be explained.
3196 : : */
3197 : 0 : err = pci_read_config_word(dev, 0x48, &rcc);
3198 [ # # ]: 0 : if (err) {
3199 : 0 : pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3200 : 0 : return;
3201 : : }
3202 : :
3203 [ # # ]: 0 : if (!(rcc & (1 << 10)))
3204 : : return;
3205 : :
3206 : 0 : rcc &= ~(1 << 10);
3207 : :
3208 : 0 : err = pci_write_config_word(dev, 0x48, rcc);
3209 [ # # ]: 0 : if (err) {
3210 : 0 : pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3211 : 0 : return;
3212 : : }
3213 : :
3214 [ # # ]: 0 : pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3215 : : }
3216 : : /* Intel 5000 series memory controllers and ports 2-7 */
3217 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3218 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3219 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3220 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3221 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3222 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3223 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3224 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3225 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3226 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3227 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3228 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3229 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3230 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3231 : : /* Intel 5100 series memory controllers and ports 2-7 */
3232 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3233 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3234 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3235 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3236 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3237 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3238 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3239 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3240 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3241 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3242 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3243 : :
3244 : : /*
3245 : : * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3246 : : * To work around this, query the size it should be configured to by the
3247 : : * device and modify the resource end to correspond to this new size.
3248 : : */
3249 : 0 : static void quirk_intel_ntb(struct pci_dev *dev)
3250 : : {
3251 : 0 : int rc;
3252 : 0 : u8 val;
3253 : :
3254 : 0 : rc = pci_read_config_byte(dev, 0x00D0, &val);
3255 [ # # ]: 0 : if (rc)
3256 : 0 : return;
3257 : :
3258 : 0 : dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3259 : :
3260 : 0 : rc = pci_read_config_byte(dev, 0x00D1, &val);
3261 [ # # ]: 0 : if (rc)
3262 : : return;
3263 : :
3264 : 0 : dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3265 : : }
3266 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3267 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3268 : :
3269 : : /*
3270 : : * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3271 : : * though no one is handling them (e.g., if the i915 driver is never
3272 : : * loaded). Additionally the interrupt destination is not set up properly
3273 : : * and the interrupt ends up -somewhere-.
3274 : : *
3275 : : * These spurious interrupts are "sticky" and the kernel disables the
3276 : : * (shared) interrupt line after 100,000+ generated interrupts.
3277 : : *
3278 : : * Fix it by disabling the still enabled interrupts. This resolves crashes
3279 : : * often seen on monitor unplug.
3280 : : */
3281 : : #define I915_DEIER_REG 0x4400c
3282 : 0 : static void disable_igfx_irq(struct pci_dev *dev)
3283 : : {
3284 : 0 : void __iomem *regs = pci_iomap(dev, 0, 0);
3285 [ # # ]: 0 : if (regs == NULL) {
3286 : 0 : pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3287 : 0 : return;
3288 : : }
3289 : :
3290 : : /* Check if any interrupt line is still enabled */
3291 [ # # ]: 0 : if (readl(regs + I915_DEIER_REG) != 0) {
3292 : 0 : pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3293 : :
3294 : 0 : writel(0, regs + I915_DEIER_REG);
3295 : : }
3296 : :
3297 : 0 : pci_iounmap(dev, regs);
3298 : : }
3299 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3300 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3301 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3302 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3303 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3304 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3305 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3306 : :
3307 : : /*
3308 : : * PCI devices which are on Intel chips can skip the 10ms delay
3309 : : * before entering D3 mode.
3310 : : */
3311 : 0 : static void quirk_remove_d3_delay(struct pci_dev *dev)
3312 : : {
3313 : 0 : dev->d3_delay = 0;
3314 : 0 : }
3315 : : /* C600 Series devices do not need 10ms d3_delay */
3316 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3317 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3318 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3319 : : /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3320 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3321 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3322 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3323 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3324 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3325 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3326 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3327 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3328 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3329 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3330 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3331 : : /* Intel Cherrytrail devices do not need 10ms d3_delay */
3332 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3333 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3334 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3335 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3336 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3337 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3338 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3339 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3340 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3341 : :
3342 : : /*
3343 : : * Some devices may pass our check in pci_intx_mask_supported() if
3344 : : * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3345 : : * support this feature.
3346 : : */
3347 : 0 : static void quirk_broken_intx_masking(struct pci_dev *dev)
3348 : : {
3349 : 0 : dev->broken_intx_masking = 1;
3350 : 0 : }
3351 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3352 : : quirk_broken_intx_masking);
3353 : : DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3354 : : quirk_broken_intx_masking);
3355 : : DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3356 : : quirk_broken_intx_masking);
3357 : :
3358 : : /*
3359 : : * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3360 : : * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3361 : : *
3362 : : * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3363 : : */
3364 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3365 : : quirk_broken_intx_masking);
3366 : :
3367 : : /*
3368 : : * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3369 : : * DisINTx can be set but the interrupt status bit is non-functional.
3370 : : */
3371 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3372 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3373 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3374 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3375 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3376 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3377 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3378 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3379 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3380 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3381 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3382 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3383 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3384 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3385 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3386 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3387 : :
3388 : : static u16 mellanox_broken_intx_devs[] = {
3389 : : PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3390 : : PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3391 : : PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3392 : : PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3393 : : PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3394 : : PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3395 : : PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3396 : : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3397 : : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3398 : : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3399 : : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3400 : : PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3401 : : PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3402 : : PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3403 : : };
3404 : :
3405 : : #define CONNECTX_4_CURR_MAX_MINOR 99
3406 : : #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3407 : :
3408 : : /*
3409 : : * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3410 : : * If so, don't mark it as broken.
3411 : : * FW minor > 99 means older FW version format and no INTx masking support.
3412 : : * FW minor < 14 means new FW version format and no INTx masking support.
3413 : : */
3414 : 0 : static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3415 : : {
3416 : 0 : __be32 __iomem *fw_ver;
3417 : 0 : u16 fw_major;
3418 : 0 : u16 fw_minor;
3419 : 0 : u16 fw_subminor;
3420 : 0 : u32 fw_maj_min;
3421 : 0 : u32 fw_sub_min;
3422 : 0 : int i;
3423 : :
3424 [ # # ]: 0 : for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3425 [ # # ]: 0 : if (pdev->device == mellanox_broken_intx_devs[i]) {
3426 : 0 : pdev->broken_intx_masking = 1;
3427 : 0 : return;
3428 : : }
3429 : : }
3430 : :
3431 : : /*
3432 : : * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3433 : : * support so shouldn't be checked further
3434 : : */
3435 [ # # ]: 0 : if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3436 : : return;
3437 : :
3438 [ # # ]: 0 : if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3439 : : pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3440 : : return;
3441 : :
3442 : : /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3443 [ # # ]: 0 : if (pci_enable_device_mem(pdev)) {
3444 : 0 : pci_warn(pdev, "Can't enable device memory\n");
3445 : 0 : return;
3446 : : }
3447 : :
3448 : 0 : fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3449 [ # # ]: 0 : if (!fw_ver) {
3450 : 0 : pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3451 : 0 : goto out;
3452 : : }
3453 : :
3454 : : /* Reading from resource space should be 32b aligned */
3455 : 0 : fw_maj_min = ioread32be(fw_ver);
3456 : 0 : fw_sub_min = ioread32be(fw_ver + 1);
3457 : 0 : fw_major = fw_maj_min & 0xffff;
3458 : 0 : fw_minor = fw_maj_min >> 16;
3459 : 0 : fw_subminor = fw_sub_min & 0xffff;
3460 [ # # ]: 0 : if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3461 : : fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3462 [ # # ]: 0 : pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3463 : : fw_major, fw_minor, fw_subminor, pdev->device ==
3464 : : PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3465 : 0 : pdev->broken_intx_masking = 1;
3466 : : }
3467 : :
3468 : 0 : iounmap(fw_ver);
3469 : :
3470 : 0 : out:
3471 : 0 : pci_disable_device(pdev);
3472 : : }
3473 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3474 : : mellanox_check_broken_intx_masking);
3475 : :
3476 : 0 : static void quirk_no_bus_reset(struct pci_dev *dev)
3477 : : {
3478 : 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3479 : 0 : }
3480 : :
3481 : : /*
3482 : : * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3483 : : * The device will throw a Link Down error on AER-capable systems and
3484 : : * regardless of AER, config space of the device is never accessible again
3485 : : * and typically causes the system to hang or reset when access is attempted.
3486 : : * http://www.spinics.net/lists/linux-pci/msg34797.html
3487 : : */
3488 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3489 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3490 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3491 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3492 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3493 : :
3494 : : /*
3495 : : * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3496 : : * reset when used with certain child devices. After the reset, config
3497 : : * accesses to the child may fail.
3498 : : */
3499 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3500 : :
3501 : 0 : static void quirk_no_pm_reset(struct pci_dev *dev)
3502 : : {
3503 : : /*
3504 : : * We can't do a bus reset on root bus devices, but an ineffective
3505 : : * PM reset may be better than nothing.
3506 : : */
3507 [ # # ]: 0 : if (!pci_is_root_bus(dev->bus))
3508 : 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3509 : 0 : }
3510 : :
3511 : : /*
3512 : : * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3513 : : * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3514 : : * to have no effect on the device: it retains the framebuffer contents and
3515 : : * monitor sync. Advertising this support makes other layers, like VFIO,
3516 : : * assume pci_reset_function() is viable for this device. Mark it as
3517 : : * unavailable to skip it when testing reset methods.
3518 : : */
3519 : : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3520 : : PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3521 : :
3522 : : /*
3523 : : * Thunderbolt controllers with broken MSI hotplug signaling:
3524 : : * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3525 : : * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3526 : : */
3527 : 0 : static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3528 : : {
3529 [ # # ]: 0 : if (pdev->is_hotplug_bridge &&
3530 [ # # ]: 0 : (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3531 [ # # ]: 0 : pdev->revision <= 1))
3532 : 0 : pdev->no_msi = 1;
3533 : 0 : }
3534 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3535 : : quirk_thunderbolt_hotplug_msi);
3536 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3537 : : quirk_thunderbolt_hotplug_msi);
3538 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3539 : : quirk_thunderbolt_hotplug_msi);
3540 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3541 : : quirk_thunderbolt_hotplug_msi);
3542 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3543 : : quirk_thunderbolt_hotplug_msi);
3544 : :
3545 : : #ifdef CONFIG_ACPI
3546 : : /*
3547 : : * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3548 : : *
3549 : : * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3550 : : * shutdown before suspend. Otherwise the native host interface (NHI) will not
3551 : : * be present after resume if a device was plugged in before suspend.
3552 : : *
3553 : : * The Thunderbolt controller consists of a PCIe switch with downstream
3554 : : * bridges leading to the NHI and to the tunnel PCI bridges.
3555 : : *
3556 : : * This quirk cuts power to the whole chip. Therefore we have to apply it
3557 : : * during suspend_noirq of the upstream bridge.
3558 : : *
3559 : : * Power is automagically restored before resume. No action is needed.
3560 : : */
3561 : 0 : static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3562 : : {
3563 : 0 : acpi_handle bridge, SXIO, SXFP, SXLV;
3564 : :
3565 [ # # ]: 0 : if (!x86_apple_machine)
3566 : 0 : return;
3567 [ # # ]: 0 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3568 : : return;
3569 [ # # # # ]: 0 : bridge = ACPI_HANDLE(&dev->dev);
3570 [ # # ]: 0 : if (!bridge)
3571 : : return;
3572 : :
3573 : : /*
3574 : : * SXIO and SXLV are present only on machines requiring this quirk.
3575 : : * Thunderbolt bridges in external devices might have the same
3576 : : * device ID as those on the host, but they will not have the
3577 : : * associated ACPI methods. This implicitly checks that we are at
3578 : : * the right bridge.
3579 : : */
3580 [ # # ]: 0 : if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3581 [ # # ]: 0 : || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3582 [ # # ]: 0 : || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3583 : 0 : return;
3584 : 0 : pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3585 : :
3586 : : /* magic sequence */
3587 : 0 : acpi_execute_simple_method(SXIO, NULL, 1);
3588 : 0 : acpi_execute_simple_method(SXFP, NULL, 0);
3589 : 0 : msleep(300);
3590 : 0 : acpi_execute_simple_method(SXLV, NULL, 0);
3591 : 0 : acpi_execute_simple_method(SXIO, NULL, 0);
3592 : 0 : acpi_execute_simple_method(SXLV, NULL, 0);
3593 : : }
3594 : : DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3595 : : PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3596 : : quirk_apple_poweroff_thunderbolt);
3597 : :
3598 : : /*
3599 : : * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3600 : : *
3601 : : * During suspend the Thunderbolt controller is reset and all PCI
3602 : : * tunnels are lost. The NHI driver will try to reestablish all tunnels
3603 : : * during resume. We have to manually wait for the NHI since there is
3604 : : * no parent child relationship between the NHI and the tunneled
3605 : : * bridges.
3606 : : */
3607 : 0 : static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3608 : : {
3609 : 0 : struct pci_dev *sibling = NULL;
3610 : 0 : struct pci_dev *nhi = NULL;
3611 : :
3612 [ # # ]: 0 : if (!x86_apple_machine)
3613 : : return;
3614 [ # # ]: 0 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3615 : : return;
3616 : :
3617 : : /*
3618 : : * Find the NHI and confirm that we are a bridge on the Thunderbolt
3619 : : * host controller and not on a Thunderbolt endpoint.
3620 : : */
3621 : 0 : sibling = pci_get_slot(dev->bus, 0x0);
3622 [ # # ]: 0 : if (sibling == dev)
3623 : 0 : goto out; /* we are the downstream bridge to the NHI */
3624 [ # # # # ]: 0 : if (!sibling || !sibling->subordinate)
3625 : 0 : goto out;
3626 : 0 : nhi = pci_get_slot(sibling->subordinate, 0x0);
3627 [ # # ]: 0 : if (!nhi)
3628 : 0 : goto out;
3629 [ # # ]: 0 : if (nhi->vendor != PCI_VENDOR_ID_INTEL
3630 [ # # ]: 0 : || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3631 [ # # ]: 0 : nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3632 [ # # ]: 0 : nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3633 : : nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3634 [ # # ]: 0 : || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3635 : 0 : goto out;
3636 : 0 : pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3637 : 0 : device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3638 : 0 : out:
3639 : 0 : pci_dev_put(nhi);
3640 : 0 : pci_dev_put(sibling);
3641 : : }
3642 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3643 : : PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3644 : : quirk_apple_wait_for_thunderbolt);
3645 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3646 : : PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3647 : : quirk_apple_wait_for_thunderbolt);
3648 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3649 : : PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3650 : : quirk_apple_wait_for_thunderbolt);
3651 : : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3652 : : PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3653 : : quirk_apple_wait_for_thunderbolt);
3654 : : #endif
3655 : :
3656 : : /*
3657 : : * Following are device-specific reset methods which can be used to
3658 : : * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3659 : : * not available.
3660 : : */
3661 : 0 : static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3662 : : {
3663 : : /*
3664 : : * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3665 : : *
3666 : : * The 82599 supports FLR on VFs, but FLR support is reported only
3667 : : * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3668 : : * Thus we must call pcie_flr() directly without first checking if it is
3669 : : * supported.
3670 : : */
3671 [ # # ]: 0 : if (!probe)
3672 : 0 : pcie_flr(dev);
3673 : 0 : return 0;
3674 : : }
3675 : :
3676 : : #define SOUTH_CHICKEN2 0xc2004
3677 : : #define PCH_PP_STATUS 0xc7200
3678 : : #define PCH_PP_CONTROL 0xc7204
3679 : : #define MSG_CTL 0x45010
3680 : : #define NSDE_PWR_STATE 0xd0100
3681 : : #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3682 : :
3683 : 0 : static int reset_ivb_igd(struct pci_dev *dev, int probe)
3684 : : {
3685 : 0 : void __iomem *mmio_base;
3686 : 0 : unsigned long timeout;
3687 : 0 : u32 val;
3688 : :
3689 [ # # ]: 0 : if (probe)
3690 : : return 0;
3691 : :
3692 : 0 : mmio_base = pci_iomap(dev, 0, 0);
3693 [ # # ]: 0 : if (!mmio_base)
3694 : : return -ENOMEM;
3695 : :
3696 : 0 : iowrite32(0x00000002, mmio_base + MSG_CTL);
3697 : :
3698 : : /*
3699 : : * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3700 : : * driver loaded sets the right bits. However, this's a reset and
3701 : : * the bits have been set by i915 previously, so we clobber
3702 : : * SOUTH_CHICKEN2 register directly here.
3703 : : */
3704 : 0 : iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3705 : :
3706 : 0 : val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3707 : 0 : iowrite32(val, mmio_base + PCH_PP_CONTROL);
3708 : :
3709 : 0 : timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3710 : 0 : do {
3711 : 0 : val = ioread32(mmio_base + PCH_PP_STATUS);
3712 [ # # ]: 0 : if ((val & 0xb0000000) == 0)
3713 : 0 : goto reset_complete;
3714 : 0 : msleep(10);
3715 [ # # ]: 0 : } while (time_before(jiffies, timeout));
3716 : 0 : pci_warn(dev, "timeout during reset\n");
3717 : :
3718 : 0 : reset_complete:
3719 : 0 : iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3720 : :
3721 : 0 : pci_iounmap(dev, mmio_base);
3722 : 0 : return 0;
3723 : : }
3724 : :
3725 : : /* Device-specific reset method for Chelsio T4-based adapters */
3726 : 0 : static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3727 : : {
3728 : 0 : u16 old_command;
3729 : 0 : u16 msix_flags;
3730 : :
3731 : : /*
3732 : : * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3733 : : * that we have no device-specific reset method.
3734 : : */
3735 [ # # ]: 0 : if ((dev->device & 0xf000) != 0x4000)
3736 : : return -ENOTTY;
3737 : :
3738 : : /*
3739 : : * If this is the "probe" phase, return 0 indicating that we can
3740 : : * reset this device.
3741 : : */
3742 [ # # ]: 0 : if (probe)
3743 : : return 0;
3744 : :
3745 : : /*
3746 : : * T4 can wedge if there are DMAs in flight within the chip and Bus
3747 : : * Master has been disabled. We need to have it on till the Function
3748 : : * Level Reset completes. (BUS_MASTER is disabled in
3749 : : * pci_reset_function()).
3750 : : */
3751 : 0 : pci_read_config_word(dev, PCI_COMMAND, &old_command);
3752 : 0 : pci_write_config_word(dev, PCI_COMMAND,
3753 : : old_command | PCI_COMMAND_MASTER);
3754 : :
3755 : : /*
3756 : : * Perform the actual device function reset, saving and restoring
3757 : : * configuration information around the reset.
3758 : : */
3759 : 0 : pci_save_state(dev);
3760 : :
3761 : : /*
3762 : : * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3763 : : * are disabled when an MSI-X interrupt message needs to be delivered.
3764 : : * So we briefly re-enable MSI-X interrupts for the duration of the
3765 : : * FLR. The pci_restore_state() below will restore the original
3766 : : * MSI-X state.
3767 : : */
3768 : 0 : pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3769 [ # # ]: 0 : if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3770 : 0 : pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3771 : : msix_flags |
3772 : : PCI_MSIX_FLAGS_ENABLE |
3773 : : PCI_MSIX_FLAGS_MASKALL);
3774 : :
3775 : 0 : pcie_flr(dev);
3776 : :
3777 : : /*
3778 : : * Restore the configuration information (BAR values, etc.) including
3779 : : * the original PCI Configuration Space Command word, and return
3780 : : * success.
3781 : : */
3782 : 0 : pci_restore_state(dev);
3783 : 0 : pci_write_config_word(dev, PCI_COMMAND, old_command);
3784 : 0 : return 0;
3785 : : }
3786 : :
3787 : : #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3788 : : #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3789 : : #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3790 : :
3791 : : /*
3792 : : * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3793 : : * FLR where config space reads from the device return -1. We seem to be
3794 : : * able to avoid this condition if we disable the NVMe controller prior to
3795 : : * FLR. This quirk is generic for any NVMe class device requiring similar
3796 : : * assistance to quiesce the device prior to FLR.
3797 : : *
3798 : : * NVMe specification: https://nvmexpress.org/resources/specifications/
3799 : : * Revision 1.0e:
3800 : : * Chapter 2: Required and optional PCI config registers
3801 : : * Chapter 3: NVMe control registers
3802 : : * Chapter 7.3: Reset behavior
3803 : : */
3804 : 0 : static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3805 : : {
3806 : 0 : void __iomem *bar;
3807 : 0 : u16 cmd;
3808 : 0 : u32 cfg;
3809 : :
3810 [ # # # # ]: 0 : if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3811 [ # # ]: 0 : !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3812 : 0 : return -ENOTTY;
3813 : :
3814 [ # # ]: 0 : if (probe)
3815 : : return 0;
3816 : :
3817 : 0 : bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3818 [ # # ]: 0 : if (!bar)
3819 : : return -ENOTTY;
3820 : :
3821 : 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
3822 : 0 : pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3823 : :
3824 : 0 : cfg = readl(bar + NVME_REG_CC);
3825 : :
3826 : : /* Disable controller if enabled */
3827 [ # # ]: 0 : if (cfg & NVME_CC_ENABLE) {
3828 : 0 : u32 cap = readl(bar + NVME_REG_CAP);
3829 : 0 : unsigned long timeout;
3830 : :
3831 : : /*
3832 : : * Per nvme_disable_ctrl() skip shutdown notification as it
3833 : : * could complete commands to the admin queue. We only intend
3834 : : * to quiesce the device before reset.
3835 : : */
3836 : 0 : cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3837 : :
3838 : 0 : writel(cfg, bar + NVME_REG_CC);
3839 : :
3840 : : /*
3841 : : * Some controllers require an additional delay here, see
3842 : : * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3843 : : * supported by this quirk.
3844 : : */
3845 : :
3846 : : /* Cap register provides max timeout in 500ms increments */
3847 : 0 : timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3848 : :
3849 : 0 : for (;;) {
3850 : 0 : u32 status = readl(bar + NVME_REG_CSTS);
3851 : :
3852 : : /* Ready status becomes zero on disable complete */
3853 [ # # ]: 0 : if (!(status & NVME_CSTS_RDY))
3854 : : break;
3855 : :
3856 : 0 : msleep(100);
3857 : :
3858 [ # # ]: 0 : if (time_after(jiffies, timeout)) {
3859 : 0 : pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3860 : 0 : break;
3861 : : }
3862 : : }
3863 : : }
3864 : :
3865 : 0 : pci_iounmap(dev, bar);
3866 : :
3867 : 0 : pcie_flr(dev);
3868 : :
3869 : 0 : return 0;
3870 : : }
3871 : :
3872 : : /*
3873 : : * Intel DC P3700 NVMe controller will timeout waiting for ready status
3874 : : * to change after NVMe enable if the driver starts interacting with the
3875 : : * device too soon after FLR. A 250ms delay after FLR has heuristically
3876 : : * proven to produce reliably working results for device assignment cases.
3877 : : */
3878 : 0 : static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3879 : : {
3880 [ # # ]: 0 : if (!pcie_has_flr(dev))
3881 : : return -ENOTTY;
3882 : :
3883 [ # # ]: 0 : if (probe)
3884 : : return 0;
3885 : :
3886 : 0 : pcie_flr(dev);
3887 : :
3888 : 0 : msleep(250);
3889 : :
3890 : 0 : return 0;
3891 : : }
3892 : :
3893 : : static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3894 : : { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3895 : : reset_intel_82599_sfp_virtfn },
3896 : : { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3897 : : reset_ivb_igd },
3898 : : { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3899 : : reset_ivb_igd },
3900 : : { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
3901 : : { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
3902 : : { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3903 : : reset_chelsio_generic_dev },
3904 : : { 0 }
3905 : : };
3906 : :
3907 : : /*
3908 : : * These device-specific reset methods are here rather than in a driver
3909 : : * because when a host assigns a device to a guest VM, the host may need
3910 : : * to reset the device but probably doesn't have a driver for it.
3911 : : */
3912 : 21 : int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3913 : : {
3914 : 21 : const struct pci_dev_reset_methods *i;
3915 : :
3916 [ + + ]: 147 : for (i = pci_dev_reset_methods; i->reset; i++) {
3917 [ + + - + ]: 126 : if ((i->vendor == dev->vendor ||
3918 : 48 : i->vendor == (u16)PCI_ANY_ID) &&
3919 [ + - - + ]: 48 : (i->device == dev->device ||
3920 : : i->device == (u16)PCI_ANY_ID))
3921 : 0 : return i->reset(dev, probe);
3922 : : }
3923 : :
3924 : : return -ENOTTY;
3925 : : }
3926 : :
3927 : 0 : static void quirk_dma_func0_alias(struct pci_dev *dev)
3928 : : {
3929 [ # # ]: 0 : if (PCI_FUNC(dev->devfn) != 0)
3930 : 0 : pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
3931 : 0 : }
3932 : :
3933 : : /*
3934 : : * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3935 : : *
3936 : : * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3937 : : */
3938 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3939 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3940 : :
3941 : 0 : static void quirk_dma_func1_alias(struct pci_dev *dev)
3942 : : {
3943 [ # # ]: 0 : if (PCI_FUNC(dev->devfn) != 1)
3944 : 0 : pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
3945 : 0 : }
3946 : :
3947 : : /*
3948 : : * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3949 : : * SKUs function 1 is present and is a legacy IDE controller, in other
3950 : : * SKUs this function is not present, making this a ghost requester.
3951 : : * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3952 : : */
3953 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3954 : : quirk_dma_func1_alias);
3955 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3956 : : quirk_dma_func1_alias);
3957 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3958 : : quirk_dma_func1_alias);
3959 : : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3960 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3961 : : quirk_dma_func1_alias);
3962 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
3963 : : quirk_dma_func1_alias);
3964 : : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3965 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3966 : : quirk_dma_func1_alias);
3967 : : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3968 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3969 : : quirk_dma_func1_alias);
3970 : : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3971 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3972 : : quirk_dma_func1_alias);
3973 : : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
3974 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
3975 : : quirk_dma_func1_alias);
3976 : : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3977 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3978 : : quirk_dma_func1_alias);
3979 : : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
3980 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
3981 : : quirk_dma_func1_alias);
3982 : : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3983 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3984 : : quirk_dma_func1_alias);
3985 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3986 : : quirk_dma_func1_alias);
3987 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
3988 : : quirk_dma_func1_alias);
3989 : : /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3990 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3991 : : PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3992 : : quirk_dma_func1_alias);
3993 : : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3994 : : DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3995 : : 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3996 : : quirk_dma_func1_alias);
3997 : :
3998 : : /*
3999 : : * Some devices DMA with the wrong devfn, not just the wrong function.
4000 : : * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4001 : : * the alias is "fixed" and independent of the device devfn.
4002 : : *
4003 : : * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4004 : : * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4005 : : * single device on the secondary bus. In reality, the single exposed
4006 : : * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4007 : : * that provides a bridge to the internal bus of the I/O processor. The
4008 : : * controller supports private devices, which can be hidden from PCI config
4009 : : * space. In the case of the Adaptec 3405, a private device at 01.0
4010 : : * appears to be the DMA engine, which therefore needs to become a DMA
4011 : : * alias for the device.
4012 : : */
4013 : : static const struct pci_device_id fixed_dma_alias_tbl[] = {
4014 : : { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4015 : : PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4016 : : .driver_data = PCI_DEVFN(1, 0) },
4017 : : { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4018 : : PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4019 : : .driver_data = PCI_DEVFN(1, 0) },
4020 : : { 0 }
4021 : : };
4022 : :
4023 : 0 : static void quirk_fixed_dma_alias(struct pci_dev *dev)
4024 : : {
4025 : 0 : const struct pci_device_id *id;
4026 : :
4027 : 0 : id = pci_match_id(fixed_dma_alias_tbl, dev);
4028 [ # # ]: 0 : if (id)
4029 : 0 : pci_add_dma_alias(dev, id->driver_data, 1);
4030 : 0 : }
4031 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4032 : :
4033 : : /*
4034 : : * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4035 : : * using the wrong DMA alias for the device. Some of these devices can be
4036 : : * used as either forward or reverse bridges, so we need to test whether the
4037 : : * device is operating in the correct mode. We could probably apply this
4038 : : * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4039 : : * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4040 : : * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4041 : : */
4042 : 0 : static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4043 : : {
4044 [ # # ]: 0 : if (!pci_is_root_bus(pdev->bus) &&
4045 [ # # # # ]: 0 : pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4046 [ # # # # ]: 0 : !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4047 : : pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4048 : 0 : pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4049 : 0 : }
4050 : : /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4051 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4052 : : quirk_use_pcie_bridge_dma_alias);
4053 : : /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4054 : : DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4055 : : /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4056 : : DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4057 : : /* ITE 8893 has the same problem as the 8892 */
4058 : : DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4059 : : /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4060 : : DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4061 : :
4062 : : /*
4063 : : * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4064 : : * be added as aliases to the DMA device in order to allow buffer access
4065 : : * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4066 : : * programmed in the EEPROM.
4067 : : */
4068 : 0 : static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4069 : : {
4070 : 0 : pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4071 : 0 : pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4072 : 0 : pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4073 : 0 : }
4074 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4075 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4076 : :
4077 : : /*
4078 : : * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4079 : : * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4080 : : *
4081 : : * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4082 : : * when IOMMU is enabled. These aliases allow computational unit access to
4083 : : * host memory. These aliases mark the whole VCA device as one IOMMU
4084 : : * group.
4085 : : *
4086 : : * All possible slot numbers (0x20) are used, since we are unable to tell
4087 : : * what slot is used on other side. This quirk is intended for both host
4088 : : * and computational unit sides. The VCA devices have up to five functions
4089 : : * (four for DMA channels and one additional).
4090 : : */
4091 : 0 : static void quirk_pex_vca_alias(struct pci_dev *pdev)
4092 : : {
4093 : 0 : const unsigned int num_pci_slots = 0x20;
4094 : 0 : unsigned int slot;
4095 : :
4096 [ # # ]: 0 : for (slot = 0; slot < num_pci_slots; slot++)
4097 : 0 : pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4098 : 0 : }
4099 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4100 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4101 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4102 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4103 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4104 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4105 : :
4106 : : /*
4107 : : * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4108 : : * associated not at the root bus, but at a bridge below. This quirk avoids
4109 : : * generating invalid DMA aliases.
4110 : : */
4111 : 0 : static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4112 : : {
4113 : 0 : pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4114 : 0 : }
4115 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4116 : : quirk_bridge_cavm_thrx2_pcie_root);
4117 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4118 : : quirk_bridge_cavm_thrx2_pcie_root);
4119 : :
4120 : : /*
4121 : : * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4122 : : * class code. Fix it.
4123 : : */
4124 : 0 : static void quirk_tw686x_class(struct pci_dev *pdev)
4125 : : {
4126 : 0 : u32 class = pdev->class;
4127 : :
4128 : : /* Use "Multimedia controller" class */
4129 : 0 : pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4130 : 0 : pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4131 : : class, pdev->class);
4132 : 0 : }
4133 : : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4134 : : quirk_tw686x_class);
4135 : : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4136 : : quirk_tw686x_class);
4137 : : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4138 : : quirk_tw686x_class);
4139 : : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4140 : : quirk_tw686x_class);
4141 : :
4142 : : /*
4143 : : * Some devices have problems with Transaction Layer Packets with the Relaxed
4144 : : * Ordering Attribute set. Such devices should mark themselves and other
4145 : : * device drivers should check before sending TLPs with RO set.
4146 : : */
4147 : 0 : static void quirk_relaxedordering_disable(struct pci_dev *dev)
4148 : : {
4149 : 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4150 : 0 : pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4151 : 0 : }
4152 : :
4153 : : /*
4154 : : * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4155 : : * Complex have a Flow Control Credit issue which can cause performance
4156 : : * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4157 : : */
4158 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4159 : : quirk_relaxedordering_disable);
4160 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4161 : : quirk_relaxedordering_disable);
4162 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4163 : : quirk_relaxedordering_disable);
4164 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4165 : : quirk_relaxedordering_disable);
4166 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4167 : : quirk_relaxedordering_disable);
4168 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4169 : : quirk_relaxedordering_disable);
4170 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4171 : : quirk_relaxedordering_disable);
4172 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4173 : : quirk_relaxedordering_disable);
4174 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4175 : : quirk_relaxedordering_disable);
4176 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4177 : : quirk_relaxedordering_disable);
4178 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4179 : : quirk_relaxedordering_disable);
4180 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4181 : : quirk_relaxedordering_disable);
4182 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4183 : : quirk_relaxedordering_disable);
4184 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4185 : : quirk_relaxedordering_disable);
4186 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4187 : : quirk_relaxedordering_disable);
4188 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4189 : : quirk_relaxedordering_disable);
4190 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4191 : : quirk_relaxedordering_disable);
4192 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4193 : : quirk_relaxedordering_disable);
4194 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4195 : : quirk_relaxedordering_disable);
4196 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4197 : : quirk_relaxedordering_disable);
4198 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4199 : : quirk_relaxedordering_disable);
4200 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4201 : : quirk_relaxedordering_disable);
4202 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4203 : : quirk_relaxedordering_disable);
4204 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4205 : : quirk_relaxedordering_disable);
4206 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4207 : : quirk_relaxedordering_disable);
4208 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4209 : : quirk_relaxedordering_disable);
4210 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4211 : : quirk_relaxedordering_disable);
4212 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4213 : : quirk_relaxedordering_disable);
4214 : :
4215 : : /*
4216 : : * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4217 : : * where Upstream Transaction Layer Packets with the Relaxed Ordering
4218 : : * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4219 : : * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4220 : : * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4221 : : * November 10, 2010). As a result, on this platform we can't use Relaxed
4222 : : * Ordering for Upstream TLPs.
4223 : : */
4224 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4225 : : quirk_relaxedordering_disable);
4226 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4227 : : quirk_relaxedordering_disable);
4228 : : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4229 : : quirk_relaxedordering_disable);
4230 : :
4231 : : /*
4232 : : * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4233 : : * values for the Attribute as were supplied in the header of the
4234 : : * corresponding Request, except as explicitly allowed when IDO is used."
4235 : : *
4236 : : * If a non-compliant device generates a completion with a different
4237 : : * attribute than the request, the receiver may accept it (which itself
4238 : : * seems non-compliant based on sec 2.3.2), or it may handle it as a
4239 : : * Malformed TLP or an Unexpected Completion, which will probably lead to a
4240 : : * device access timeout.
4241 : : *
4242 : : * If the non-compliant device generates completions with zero attributes
4243 : : * (instead of copying the attributes from the request), we can work around
4244 : : * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4245 : : * upstream devices so they always generate requests with zero attributes.
4246 : : *
4247 : : * This affects other devices under the same Root Port, but since these
4248 : : * attributes are performance hints, there should be no functional problem.
4249 : : *
4250 : : * Note that Configuration Space accesses are never supposed to have TLP
4251 : : * Attributes, so we're safe waiting till after any Configuration Space
4252 : : * accesses to do the Root Port fixup.
4253 : : */
4254 : 0 : static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4255 : : {
4256 : 0 : struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4257 : :
4258 [ # # ]: 0 : if (!root_port) {
4259 : 0 : pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4260 : 0 : return;
4261 : : }
4262 : :
4263 [ # # ]: 0 : pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4264 : : dev_name(&pdev->dev));
4265 : 0 : pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4266 : : PCI_EXP_DEVCTL_RELAX_EN |
4267 : : PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4268 : : }
4269 : :
4270 : : /*
4271 : : * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4272 : : * Completion it generates.
4273 : : */
4274 : 0 : static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4275 : : {
4276 : : /*
4277 : : * This mask/compare operation selects for Physical Function 4 on a
4278 : : * T5. We only need to fix up the Root Port once for any of the
4279 : : * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4280 : : * 0x54xx so we use that one.
4281 : : */
4282 [ # # ]: 0 : if ((pdev->device & 0xff00) == 0x5400)
4283 : 0 : quirk_disable_root_port_attributes(pdev);
4284 : 0 : }
4285 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4286 : : quirk_chelsio_T5_disable_root_port_attributes);
4287 : :
4288 : : /*
4289 : : * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4290 : : * by a device
4291 : : * @acs_ctrl_req: Bitmask of desired ACS controls
4292 : : * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4293 : : * the hardware design
4294 : : *
4295 : : * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4296 : : * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4297 : : * caller desires. Return 0 otherwise.
4298 : : */
4299 : 0 : static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4300 : : {
4301 : 0 : if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4302 : 0 : return 1;
4303 : : return 0;
4304 : : }
4305 : :
4306 : : /*
4307 : : * AMD has indicated that the devices below do not support peer-to-peer
4308 : : * in any system where they are found in the southbridge with an AMD
4309 : : * IOMMU in the system. Multifunction devices that do not support
4310 : : * peer-to-peer between functions can claim to support a subset of ACS.
4311 : : * Such devices effectively enable request redirect (RR) and completion
4312 : : * redirect (CR) since all transactions are redirected to the upstream
4313 : : * root complex.
4314 : : *
4315 : : * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4316 : : * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4317 : : * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4318 : : *
4319 : : * 1002:4385 SBx00 SMBus Controller
4320 : : * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4321 : : * 1002:4383 SBx00 Azalia (Intel HDA)
4322 : : * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4323 : : * 1002:4384 SBx00 PCI to PCI Bridge
4324 : : * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4325 : : *
4326 : : * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4327 : : *
4328 : : * 1022:780f [AMD] FCH PCI Bridge
4329 : : * 1022:7809 [AMD] FCH USB OHCI Controller
4330 : : */
4331 : 0 : static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4332 : : {
4333 : : #ifdef CONFIG_ACPI
4334 : 0 : struct acpi_table_header *header = NULL;
4335 : 0 : acpi_status status;
4336 : :
4337 : : /* Targeting multifunction devices on the SB (appears on root bus) */
4338 [ # # # # ]: 0 : if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4339 : : return -ENODEV;
4340 : :
4341 : : /* The IVRS table describes the AMD IOMMU */
4342 : 0 : status = acpi_get_table("IVRS", 0, &header);
4343 [ # # ]: 0 : if (ACPI_FAILURE(status))
4344 : : return -ENODEV;
4345 : :
4346 : : /* Filter out flags not applicable to multifunction */
4347 : 0 : acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4348 : :
4349 [ # # ]: 0 : return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4350 : : #else
4351 : : return -ENODEV;
4352 : : #endif
4353 : : }
4354 : :
4355 : 0 : static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4356 : : {
4357 [ # # ]: 0 : if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4358 : : return false;
4359 : :
4360 [ # # ]: 0 : switch (dev->device) {
4361 : : /*
4362 : : * Effectively selects all downstream ports for whole ThunderX1
4363 : : * (which represents 8 SoCs).
4364 : : */
4365 : : case 0xa000 ... 0xa7ff: /* ThunderX1 */
4366 : : case 0xaf84: /* ThunderX2 */
4367 : : case 0xb884: /* ThunderX3 */
4368 : : return true;
4369 : : default:
4370 : : return false;
4371 : : }
4372 : : }
4373 : :
4374 : 0 : static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4375 : : {
4376 [ # # ]: 0 : if (!pci_quirk_cavium_acs_match(dev))
4377 : : return -ENOTTY;
4378 : :
4379 : : /*
4380 : : * Cavium Root Ports don't advertise an ACS capability. However,
4381 : : * the RTL internally implements similar protection as if ACS had
4382 : : * Source Validation, Request Redirection, Completion Redirection,
4383 : : * and Upstream Forwarding features enabled. Assert that the
4384 : : * hardware implements and enables equivalent ACS functionality for
4385 : : * these flags.
4386 : : */
4387 [ # # ]: 0 : return pci_acs_ctrl_enabled(acs_flags,
4388 : : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4389 : : }
4390 : :
4391 : 0 : static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4392 : : {
4393 : : /*
4394 : : * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4395 : : * transactions with others, allowing masking out these bits as if they
4396 : : * were unimplemented in the ACS capability.
4397 : : */
4398 [ # # ]: 0 : return pci_acs_ctrl_enabled(acs_flags,
4399 : : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4400 : : }
4401 : :
4402 : : /*
4403 : : * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4404 : : * transactions and validate bus numbers in requests, but do not provide an
4405 : : * actual PCIe ACS capability. This is the list of device IDs known to fall
4406 : : * into that category as provided by Intel in Red Hat bugzilla 1037684.
4407 : : */
4408 : : static const u16 pci_quirk_intel_pch_acs_ids[] = {
4409 : : /* Ibexpeak PCH */
4410 : : 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4411 : : 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4412 : : /* Cougarpoint PCH */
4413 : : 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4414 : : 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4415 : : /* Pantherpoint PCH */
4416 : : 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4417 : : 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4418 : : /* Lynxpoint-H PCH */
4419 : : 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4420 : : 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4421 : : /* Lynxpoint-LP PCH */
4422 : : 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4423 : : 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4424 : : /* Wildcat PCH */
4425 : : 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4426 : : 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4427 : : /* Patsburg (X79) PCH */
4428 : : 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4429 : : /* Wellsburg (X99) PCH */
4430 : : 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4431 : : 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4432 : : /* Lynx Point (9 series) PCH */
4433 : : 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4434 : : };
4435 : :
4436 : 0 : static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4437 : : {
4438 : 0 : int i;
4439 : :
4440 : : /* Filter out a few obvious non-matches first */
4441 [ # # # # ]: 0 : if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4442 : : return false;
4443 : :
4444 [ # # # # ]: 0 : for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4445 [ # # # # ]: 0 : if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4446 : : return true;
4447 : :
4448 : : return false;
4449 : : }
4450 : :
4451 : 0 : static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4452 : : {
4453 [ # # # # ]: 0 : if (!pci_quirk_intel_pch_acs_match(dev))
4454 : : return -ENOTTY;
4455 : :
4456 [ # # ]: 0 : if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4457 [ # # ]: 0 : return pci_acs_ctrl_enabled(acs_flags,
4458 : : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4459 : :
4460 [ # # ]: 0 : return pci_acs_ctrl_enabled(acs_flags, 0);
4461 : : }
4462 : :
4463 : : /*
4464 : : * These QCOM Root Ports do provide ACS-like features to disable peer
4465 : : * transactions and validate bus numbers in requests, but do not provide an
4466 : : * actual PCIe ACS capability. Hardware supports source validation but it
4467 : : * will report the issue as Completer Abort instead of ACS Violation.
4468 : : * Hardware doesn't support peer-to-peer and each Root Port is a Root
4469 : : * Complex with unique segment numbers. It is not possible for one Root
4470 : : * Port to pass traffic to another Root Port. All PCIe transactions are
4471 : : * terminated inside the Root Port.
4472 : : */
4473 : 0 : static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4474 : : {
4475 [ # # ]: 0 : return pci_acs_ctrl_enabled(acs_flags,
4476 : : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4477 : : }
4478 : :
4479 : 0 : static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4480 : : {
4481 [ # # ]: 0 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4482 : : return -ENOTTY;
4483 : :
4484 : : /*
4485 : : * Amazon's Annapurna Labs root ports don't include an ACS capability,
4486 : : * but do include ACS-like functionality. The hardware doesn't support
4487 : : * peer-to-peer transactions via the root port and each has a unique
4488 : : * segment number.
4489 : : *
4490 : : * Additionally, the root ports cannot send traffic to each other.
4491 : : */
4492 : 0 : acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4493 : :
4494 : 0 : return acs_flags ? 0 : 1;
4495 : : }
4496 : :
4497 : : /*
4498 : : * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4499 : : * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4500 : : * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4501 : : * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4502 : : * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4503 : : * control register is at offset 8 instead of 6 and we should probably use
4504 : : * dword accesses to them. This applies to the following PCI Device IDs, as
4505 : : * found in volume 1 of the datasheet[2]:
4506 : : *
4507 : : * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4508 : : * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4509 : : *
4510 : : * N.B. This doesn't fix what lspci shows.
4511 : : *
4512 : : * The 100 series chipset specification update includes this as errata #23[3].
4513 : : *
4514 : : * The 200 series chipset (Union Point) has the same bug according to the
4515 : : * specification update (Intel 200 Series Chipset Family Platform Controller
4516 : : * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4517 : : * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4518 : : * chipset include:
4519 : : *
4520 : : * 0xa290-0xa29f PCI Express Root port #{0-16}
4521 : : * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4522 : : *
4523 : : * Mobile chipsets are also affected, 7th & 8th Generation
4524 : : * Specification update confirms ACS errata 22, status no fix: (7th Generation
4525 : : * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4526 : : * Processor Family I/O for U Quad Core Platforms Specification Update,
4527 : : * August 2017, Revision 002, Document#: 334660-002)[6]
4528 : : * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4529 : : * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4530 : : * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4531 : : *
4532 : : * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4533 : : *
4534 : : * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4535 : : * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4536 : : * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4537 : : * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4538 : : * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4539 : : * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4540 : : * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4541 : : */
4542 : 0 : static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4543 : : {
4544 [ # # # # ]: 0 : if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4545 : : return false;
4546 : :
4547 [ # # ]: 0 : switch (dev->device) {
4548 : : case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4549 : : case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4550 : : case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4551 : : return true;
4552 : : }
4553 : :
4554 : 0 : return false;
4555 : : }
4556 : :
4557 : : #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4558 : :
4559 : 0 : static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4560 : : {
4561 : 0 : int pos;
4562 : 0 : u32 cap, ctrl;
4563 : :
4564 [ # # ]: 0 : if (!pci_quirk_intel_spt_pch_acs_match(dev))
4565 : : return -ENOTTY;
4566 : :
4567 : 0 : pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4568 [ # # ]: 0 : if (!pos)
4569 : : return -ENOTTY;
4570 : :
4571 : : /* see pci_acs_flags_enabled() */
4572 : 0 : pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4573 : 0 : acs_flags &= (cap | PCI_ACS_EC);
4574 : :
4575 : 0 : pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4576 : :
4577 [ # # ]: 0 : return pci_acs_ctrl_enabled(acs_flags, ctrl);
4578 : : }
4579 : :
4580 : 0 : static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4581 : : {
4582 : : /*
4583 : : * SV, TB, and UF are not relevant to multifunction endpoints.
4584 : : *
4585 : : * Multifunction devices are only required to implement RR, CR, and DT
4586 : : * in their ACS capability if they support peer-to-peer transactions.
4587 : : * Devices matching this quirk have been verified by the vendor to not
4588 : : * perform peer-to-peer with other functions, allowing us to mask out
4589 : : * these bits as if they were unimplemented in the ACS capability.
4590 : : */
4591 [ # # ]: 0 : return pci_acs_ctrl_enabled(acs_flags,
4592 : : PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4593 : : PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4594 : : }
4595 : :
4596 : 0 : static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4597 : : {
4598 : : /*
4599 : : * iProc PAXB Root Ports don't advertise an ACS capability, but
4600 : : * they do not allow peer-to-peer transactions between Root Ports.
4601 : : * Allow each Root Port to be in a separate IOMMU group by masking
4602 : : * SV/RR/CR/UF bits.
4603 : : */
4604 [ # # ]: 0 : return pci_acs_ctrl_enabled(acs_flags,
4605 : : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4606 : : }
4607 : :
4608 : : static const struct pci_dev_acs_enabled {
4609 : : u16 vendor;
4610 : : u16 device;
4611 : : int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4612 : : } pci_dev_acs_enabled[] = {
4613 : : { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4614 : : { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4615 : : { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4616 : : { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4617 : : { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4618 : : { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4619 : : { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4620 : : { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4621 : : { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4622 : : { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4623 : : { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4624 : : { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4625 : : { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4626 : : { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4627 : : { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4628 : : { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4629 : : { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4630 : : { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4631 : : { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4632 : : { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4633 : : { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4634 : : { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4635 : : { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4636 : : { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4637 : : { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4638 : : { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4639 : : { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4640 : : { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4641 : : { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4642 : : { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4643 : : { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4644 : : /* 82580 */
4645 : : { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4646 : : { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4647 : : { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4648 : : { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4649 : : { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4650 : : { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4651 : : { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4652 : : /* 82576 */
4653 : : { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4654 : : { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4655 : : { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4656 : : { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4657 : : { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4658 : : { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4659 : : { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4660 : : { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4661 : : /* 82575 */
4662 : : { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4663 : : { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4664 : : { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4665 : : /* I350 */
4666 : : { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4667 : : { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4668 : : { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4669 : : { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4670 : : /* 82571 (Quads omitted due to non-ACS switch) */
4671 : : { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4672 : : { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4673 : : { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4674 : : { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4675 : : /* I219 */
4676 : : { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4677 : : { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4678 : : /* QCOM QDF2xxx root ports */
4679 : : { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4680 : : { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4681 : : /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4682 : : { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4683 : : /* Intel PCH root ports */
4684 : : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4685 : : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4686 : : { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4687 : : { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4688 : : /* Cavium ThunderX */
4689 : : { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4690 : : /* APM X-Gene */
4691 : : { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4692 : : /* Ampere Computing */
4693 : : { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4694 : : { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4695 : : { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4696 : : { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4697 : : { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4698 : : { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4699 : : { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4700 : : { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4701 : : { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4702 : : /* Amazon Annapurna Labs */
4703 : : { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4704 : : { 0 }
4705 : : };
4706 : :
4707 : : /*
4708 : : * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4709 : : * @dev: PCI device
4710 : : * @acs_flags: Bitmask of desired ACS controls
4711 : : *
4712 : : * Returns:
4713 : : * -ENOTTY: No quirk applies to this device; we can't tell whether the
4714 : : * device provides the desired controls
4715 : : * 0: Device does not provide all the desired controls
4716 : : * >0: Device provides all the controls in @acs_flags
4717 : : */
4718 : 0 : int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4719 : : {
4720 : 0 : const struct pci_dev_acs_enabled *i;
4721 : 0 : int ret;
4722 : :
4723 : : /*
4724 : : * Allow devices that do not expose standard PCIe ACS capabilities
4725 : : * or control to indicate their support here. Multi-function express
4726 : : * devices which do not allow internal peer-to-peer between functions,
4727 : : * but do not implement PCIe ACS may wish to return true here.
4728 : : */
4729 [ # # ]: 0 : for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4730 [ # # # # ]: 0 : if ((i->vendor == dev->vendor ||
4731 : 0 : i->vendor == (u16)PCI_ANY_ID) &&
4732 [ # # # # ]: 0 : (i->device == dev->device ||
4733 : : i->device == (u16)PCI_ANY_ID)) {
4734 : 0 : ret = i->acs_enabled(dev, acs_flags);
4735 [ # # ]: 0 : if (ret >= 0)
4736 : 0 : return ret;
4737 : : }
4738 : : }
4739 : :
4740 : : return -ENOTTY;
4741 : : }
4742 : :
4743 : : /* Config space offset of Root Complex Base Address register */
4744 : : #define INTEL_LPC_RCBA_REG 0xf0
4745 : : /* 31:14 RCBA address */
4746 : : #define INTEL_LPC_RCBA_MASK 0xffffc000
4747 : : /* RCBA Enable */
4748 : : #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4749 : :
4750 : : /* Backbone Scratch Pad Register */
4751 : : #define INTEL_BSPR_REG 0x1104
4752 : : /* Backbone Peer Non-Posted Disable */
4753 : : #define INTEL_BSPR_REG_BPNPD (1 << 8)
4754 : : /* Backbone Peer Posted Disable */
4755 : : #define INTEL_BSPR_REG_BPPD (1 << 9)
4756 : :
4757 : : /* Upstream Peer Decode Configuration Register */
4758 : : #define INTEL_UPDCR_REG 0x1014
4759 : : /* 5:0 Peer Decode Enable bits */
4760 : : #define INTEL_UPDCR_REG_MASK 0x3f
4761 : :
4762 : 0 : static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4763 : : {
4764 : 0 : u32 rcba, bspr, updcr;
4765 : 0 : void __iomem *rcba_mem;
4766 : :
4767 : : /*
4768 : : * Read the RCBA register from the LPC (D31:F0). PCH root ports
4769 : : * are D28:F* and therefore get probed before LPC, thus we can't
4770 : : * use pci_get_slot()/pci_read_config_dword() here.
4771 : : */
4772 : 0 : pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4773 : : INTEL_LPC_RCBA_REG, &rcba);
4774 [ # # ]: 0 : if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4775 : : return -EINVAL;
4776 : :
4777 : 0 : rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
4778 : : PAGE_ALIGN(INTEL_UPDCR_REG));
4779 [ # # ]: 0 : if (!rcba_mem)
4780 : : return -ENOMEM;
4781 : :
4782 : : /*
4783 : : * The BSPR can disallow peer cycles, but it's set by soft strap and
4784 : : * therefore read-only. If both posted and non-posted peer cycles are
4785 : : * disallowed, we're ok. If either are allowed, then we need to use
4786 : : * the UPDCR to disable peer decodes for each port. This provides the
4787 : : * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4788 : : */
4789 : 0 : bspr = readl(rcba_mem + INTEL_BSPR_REG);
4790 : 0 : bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4791 [ # # ]: 0 : if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4792 : 0 : updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4793 [ # # ]: 0 : if (updcr & INTEL_UPDCR_REG_MASK) {
4794 : 0 : pci_info(dev, "Disabling UPDCR peer decodes\n");
4795 : 0 : updcr &= ~INTEL_UPDCR_REG_MASK;
4796 : 0 : writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4797 : : }
4798 : : }
4799 : :
4800 : 0 : iounmap(rcba_mem);
4801 : 0 : return 0;
4802 : : }
4803 : :
4804 : : /* Miscellaneous Port Configuration register */
4805 : : #define INTEL_MPC_REG 0xd8
4806 : : /* MPC: Invalid Receive Bus Number Check Enable */
4807 : : #define INTEL_MPC_REG_IRBNCE (1 << 26)
4808 : :
4809 : 0 : static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4810 : : {
4811 : 0 : u32 mpc;
4812 : :
4813 : : /*
4814 : : * When enabled, the IRBNCE bit of the MPC register enables the
4815 : : * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4816 : : * ensures that requester IDs fall within the bus number range
4817 : : * of the bridge. Enable if not already.
4818 : : */
4819 : 0 : pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4820 [ # # ]: 0 : if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4821 : 0 : pci_info(dev, "Enabling MPC IRBNCE\n");
4822 : 0 : mpc |= INTEL_MPC_REG_IRBNCE;
4823 : 0 : pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4824 : : }
4825 : 0 : }
4826 : :
4827 : 0 : static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4828 : : {
4829 [ # # # # ]: 0 : if (!pci_quirk_intel_pch_acs_match(dev))
4830 : : return -ENOTTY;
4831 : :
4832 [ # # ]: 0 : if (pci_quirk_enable_intel_lpc_acs(dev)) {
4833 : 0 : pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4834 : 0 : return 0;
4835 : : }
4836 : :
4837 : 0 : pci_quirk_enable_intel_rp_mpc_acs(dev);
4838 : :
4839 : 0 : dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4840 : :
4841 : 0 : pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
4842 : :
4843 : 0 : return 0;
4844 : : }
4845 : :
4846 : 0 : static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4847 : : {
4848 : 0 : int pos;
4849 : 0 : u32 cap, ctrl;
4850 : :
4851 [ # # ]: 0 : if (!pci_quirk_intel_spt_pch_acs_match(dev))
4852 : : return -ENOTTY;
4853 : :
4854 : 0 : pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4855 [ # # ]: 0 : if (!pos)
4856 : : return -ENOTTY;
4857 : :
4858 : 0 : pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4859 : 0 : pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4860 : :
4861 : 0 : ctrl |= (cap & PCI_ACS_SV);
4862 : 0 : ctrl |= (cap & PCI_ACS_RR);
4863 : 0 : ctrl |= (cap & PCI_ACS_CR);
4864 : 0 : ctrl |= (cap & PCI_ACS_UF);
4865 : :
4866 : 0 : pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4867 : :
4868 : 0 : pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
4869 : :
4870 : 0 : return 0;
4871 : : }
4872 : :
4873 : 0 : static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
4874 : : {
4875 : 0 : int pos;
4876 : 0 : u32 cap, ctrl;
4877 : :
4878 [ # # ]: 0 : if (!pci_quirk_intel_spt_pch_acs_match(dev))
4879 : : return -ENOTTY;
4880 : :
4881 : 0 : pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4882 [ # # ]: 0 : if (!pos)
4883 : : return -ENOTTY;
4884 : :
4885 : 0 : pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4886 : 0 : pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4887 : :
4888 : 0 : ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
4889 : :
4890 : 0 : pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4891 : :
4892 : 0 : pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
4893 : :
4894 : 0 : return 0;
4895 : : }
4896 : :
4897 : : static const struct pci_dev_acs_ops {
4898 : : u16 vendor;
4899 : : u16 device;
4900 : : int (*enable_acs)(struct pci_dev *dev);
4901 : : int (*disable_acs_redir)(struct pci_dev *dev);
4902 : : } pci_dev_acs_ops[] = {
4903 : : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
4904 : : .enable_acs = pci_quirk_enable_intel_pch_acs,
4905 : : },
4906 : : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
4907 : : .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
4908 : : .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
4909 : : },
4910 : : };
4911 : :
4912 : 0 : int pci_dev_specific_enable_acs(struct pci_dev *dev)
4913 : : {
4914 : 0 : const struct pci_dev_acs_ops *p;
4915 : 0 : int i, ret;
4916 : :
4917 [ # # ]: 0 : for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
4918 : 0 : p = &pci_dev_acs_ops[i];
4919 [ # # # # ]: 0 : if ((p->vendor == dev->vendor ||
4920 : 0 : p->vendor == (u16)PCI_ANY_ID) &&
4921 [ # # # # ]: 0 : (p->device == dev->device ||
4922 : 0 : p->device == (u16)PCI_ANY_ID) &&
4923 [ # # ]: 0 : p->enable_acs) {
4924 : 0 : ret = p->enable_acs(dev);
4925 [ # # ]: 0 : if (ret >= 0)
4926 : 0 : return ret;
4927 : : }
4928 : : }
4929 : :
4930 : : return -ENOTTY;
4931 : : }
4932 : :
4933 : 0 : int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
4934 : : {
4935 : 0 : const struct pci_dev_acs_ops *p;
4936 : 0 : int i, ret;
4937 : :
4938 [ # # ]: 0 : for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
4939 : 0 : p = &pci_dev_acs_ops[i];
4940 [ # # # # ]: 0 : if ((p->vendor == dev->vendor ||
4941 : 0 : p->vendor == (u16)PCI_ANY_ID) &&
4942 [ # # # # ]: 0 : (p->device == dev->device ||
4943 : 0 : p->device == (u16)PCI_ANY_ID) &&
4944 [ # # ]: 0 : p->disable_acs_redir) {
4945 : 0 : ret = p->disable_acs_redir(dev);
4946 [ # # ]: 0 : if (ret >= 0)
4947 : 0 : return ret;
4948 : : }
4949 : : }
4950 : :
4951 : : return -ENOTTY;
4952 : : }
4953 : :
4954 : : /*
4955 : : * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
4956 : : * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4957 : : * Next Capability pointer in the MSI Capability Structure should point to
4958 : : * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4959 : : * the list.
4960 : : */
4961 : 0 : static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4962 : : {
4963 : 0 : int pos, i = 0;
4964 : 0 : u8 next_cap;
4965 : 0 : u16 reg16, *cap;
4966 : 0 : struct pci_cap_saved_state *state;
4967 : :
4968 : : /* Bail if the hardware bug is fixed */
4969 [ # # # # ]: 0 : if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4970 : 0 : return;
4971 : :
4972 : : /* Bail if MSI Capability Structure is not found for some reason */
4973 : 0 : pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4974 [ # # ]: 0 : if (!pos)
4975 : : return;
4976 : :
4977 : : /*
4978 : : * Bail if Next Capability pointer in the MSI Capability Structure
4979 : : * is not the expected incorrect 0x00.
4980 : : */
4981 : 0 : pci_read_config_byte(pdev, pos + 1, &next_cap);
4982 [ # # ]: 0 : if (next_cap)
4983 : : return;
4984 : :
4985 : : /*
4986 : : * PCIe Capability Structure is expected to be at 0x50 and should
4987 : : * terminate the list (Next Capability pointer is 0x00). Verify
4988 : : * Capability Id and Next Capability pointer is as expected.
4989 : : * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4990 : : * to correctly set kernel data structures which have already been
4991 : : * set incorrectly due to the hardware bug.
4992 : : */
4993 : 0 : pos = 0x50;
4994 : 0 : pci_read_config_word(pdev, pos, ®16);
4995 [ # # ]: 0 : if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4996 : 0 : u32 status;
4997 : : #ifndef PCI_EXP_SAVE_REGS
4998 : : #define PCI_EXP_SAVE_REGS 7
4999 : : #endif
5000 : 0 : int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5001 : :
5002 : 0 : pdev->pcie_cap = pos;
5003 : 0 : pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5004 : 0 : pdev->pcie_flags_reg = reg16;
5005 : 0 : pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5006 : 0 : pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5007 : :
5008 : 0 : pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5009 [ # # ]: 0 : if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5010 [ # # ]: 0 : PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5011 : 0 : pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5012 : :
5013 [ # # ]: 0 : if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5014 : 0 : return;
5015 : :
5016 : : /* Save PCIe cap */
5017 : 0 : state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5018 [ # # ]: 0 : if (!state)
5019 : : return;
5020 : :
5021 : 0 : state->cap.cap_nr = PCI_CAP_ID_EXP;
5022 : 0 : state->cap.cap_extended = 0;
5023 : 0 : state->cap.size = size;
5024 : 0 : cap = (u16 *)&state->cap.data[0];
5025 : 0 : pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5026 : 0 : pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5027 : 0 : pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5028 : 0 : pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5029 : 0 : pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5030 : 0 : pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5031 : 0 : pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5032 [ # # ]: 0 : hlist_add_head(&state->next, &pdev->saved_cap_space);
5033 : : }
5034 : : }
5035 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5036 : :
5037 : : /* FLR may cause some 82579 devices to hang */
5038 : 0 : static void quirk_intel_no_flr(struct pci_dev *dev)
5039 : : {
5040 : 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5041 : 0 : }
5042 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
5043 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
5044 : :
5045 : 0 : static void quirk_no_ext_tags(struct pci_dev *pdev)
5046 : : {
5047 : 0 : struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5048 : :
5049 [ # # ]: 0 : if (!bridge)
5050 : : return;
5051 : :
5052 : 0 : bridge->no_ext_tags = 1;
5053 : 0 : pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5054 : :
5055 : 0 : pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5056 : : }
5057 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5058 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5059 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5060 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5061 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5062 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5063 : : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5064 : :
5065 : : #ifdef CONFIG_PCI_ATS
5066 : : /*
5067 : : * Some devices require additional driver setup to enable ATS. Don't use
5068 : : * ATS for those devices as ATS will be enabled before the driver has had a
5069 : : * chance to load and configure the device.
5070 : : */
5071 : 0 : static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5072 : : {
5073 [ # # # # ]: 0 : if (pdev->device == 0x7340 && pdev->revision != 0xc5)
5074 : : return;
5075 : :
5076 : 0 : pci_info(pdev, "disabling ATS\n");
5077 : 0 : pdev->ats_cap = 0;
5078 : : }
5079 : :
5080 : : /* AMD Stoney platform GPU */
5081 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5082 : : /* AMD Iceland dGPU */
5083 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5084 : : /* AMD Navi14 dGPU */
5085 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5086 : : #endif /* CONFIG_PCI_ATS */
5087 : :
5088 : : /* Freescale PCIe doesn't support MSI in RC mode */
5089 : 0 : static void quirk_fsl_no_msi(struct pci_dev *pdev)
5090 : : {
5091 [ # # ]: 0 : if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5092 : 0 : pdev->no_msi = 1;
5093 : 0 : }
5094 : : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5095 : :
5096 : : /*
5097 : : * Although not allowed by the spec, some multi-function devices have
5098 : : * dependencies of one function (consumer) on another (supplier). For the
5099 : : * consumer to work in D0, the supplier must also be in D0. Create a
5100 : : * device link from the consumer to the supplier to enforce this
5101 : : * dependency. Runtime PM is allowed by default on the consumer to prevent
5102 : : * it from permanently keeping the supplier awake.
5103 : : */
5104 : 0 : static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5105 : : unsigned int supplier, unsigned int class,
5106 : : unsigned int class_shift)
5107 : : {
5108 : 0 : struct pci_dev *supplier_pdev;
5109 : :
5110 [ # # ]: 0 : if (PCI_FUNC(pdev->devfn) != consumer)
5111 : : return;
5112 : :
5113 : 0 : supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5114 : 0 : pdev->bus->number,
5115 : 0 : PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5116 [ # # # # ]: 0 : if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5117 : 0 : pci_dev_put(supplier_pdev);
5118 : 0 : return;
5119 : : }
5120 : :
5121 [ # # ]: 0 : if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5122 : : DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5123 [ # # ]: 0 : pci_info(pdev, "D0 power state depends on %s\n",
5124 : : pci_name(supplier_pdev));
5125 : : else
5126 [ # # ]: 0 : pci_err(pdev, "Cannot enforce power dependency on %s\n",
5127 : : pci_name(supplier_pdev));
5128 : :
5129 : 0 : pm_runtime_allow(&pdev->dev);
5130 : 0 : pci_dev_put(supplier_pdev);
5131 : : }
5132 : :
5133 : : /*
5134 : : * Create device link for GPUs with integrated HDA controller for streaming
5135 : : * audio to attached displays.
5136 : : */
5137 : 0 : static void quirk_gpu_hda(struct pci_dev *hda)
5138 : : {
5139 : 0 : pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5140 : 0 : }
5141 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5142 : : PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5143 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5144 : : PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5145 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5146 : : PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5147 : :
5148 : : /*
5149 : : * Create device link for NVIDIA GPU with integrated USB xHCI Host
5150 : : * controller to VGA.
5151 : : */
5152 : 0 : static void quirk_gpu_usb(struct pci_dev *usb)
5153 : : {
5154 : 0 : pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5155 : 0 : }
5156 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5157 : : PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5158 : :
5159 : : /*
5160 : : * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
5161 : : * to VGA. Currently there is no class code defined for UCSI device over PCI
5162 : : * so using UNKNOWN class for now and it will be updated when UCSI
5163 : : * over PCI gets a class code.
5164 : : */
5165 : : #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5166 : 0 : static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5167 : : {
5168 : 0 : pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5169 : 0 : }
5170 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5171 : : PCI_CLASS_SERIAL_UNKNOWN, 8,
5172 : : quirk_gpu_usb_typec_ucsi);
5173 : :
5174 : : /*
5175 : : * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5176 : : * disabled. https://devtalk.nvidia.com/default/topic/1024022
5177 : : */
5178 : 0 : static void quirk_nvidia_hda(struct pci_dev *gpu)
5179 : : {
5180 : 0 : u8 hdr_type;
5181 : 0 : u32 val;
5182 : :
5183 : : /* There was no integrated HDA controller before MCP89 */
5184 [ # # ]: 0 : if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5185 : 0 : return;
5186 : :
5187 : : /* Bit 25 at offset 0x488 enables the HDA controller */
5188 : 0 : pci_read_config_dword(gpu, 0x488, &val);
5189 [ # # ]: 0 : if (val & BIT(25))
5190 : : return;
5191 : :
5192 : 0 : pci_info(gpu, "Enabling HDA controller\n");
5193 : 0 : pci_write_config_dword(gpu, 0x488, val | BIT(25));
5194 : :
5195 : : /* The GPU becomes a multi-function device when the HDA is enabled */
5196 : 0 : pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5197 : 0 : gpu->multifunction = !!(hdr_type & 0x80);
5198 : : }
5199 : : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5200 : : PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5201 : : DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5202 : : PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5203 : :
5204 : : /*
5205 : : * Some IDT switches incorrectly flag an ACS Source Validation error on
5206 : : * completions for config read requests even though PCIe r4.0, sec
5207 : : * 6.12.1.1, says that completions are never affected by ACS Source
5208 : : * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5209 : : *
5210 : : * Item #36 - Downstream port applies ACS Source Validation to Completions
5211 : : * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5212 : : * completions are never affected by ACS Source Validation. However,
5213 : : * completions received by a downstream port of the PCIe switch from a
5214 : : * device that has not yet captured a PCIe bus number are incorrectly
5215 : : * dropped by ACS Source Validation by the switch downstream port.
5216 : : *
5217 : : * The workaround suggested by IDT is to issue a config write to the
5218 : : * downstream device before issuing the first config read. This allows the
5219 : : * downstream device to capture its bus and device numbers (see PCIe r4.0,
5220 : : * sec 2.2.9), thus avoiding the ACS error on the completion.
5221 : : *
5222 : : * However, we don't know when the device is ready to accept the config
5223 : : * write, so we do config reads until we receive a non-Config Request Retry
5224 : : * Status, then do the config write.
5225 : : *
5226 : : * To avoid hitting the erratum when doing the config reads, we disable ACS
5227 : : * SV around this process.
5228 : : */
5229 : 0 : int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5230 : : {
5231 : 0 : int pos;
5232 : 0 : u16 ctrl = 0;
5233 : 0 : bool found;
5234 : 0 : struct pci_dev *bridge = bus->self;
5235 : :
5236 : 0 : pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);
5237 : :
5238 : : /* Disable ACS SV before initial config reads */
5239 [ # # ]: 0 : if (pos) {
5240 : 0 : pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5241 [ # # ]: 0 : if (ctrl & PCI_ACS_SV)
5242 : 0 : pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5243 : : ctrl & ~PCI_ACS_SV);
5244 : : }
5245 : :
5246 : 0 : found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5247 : :
5248 : : /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5249 [ # # ]: 0 : if (found)
5250 : 0 : pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5251 : :
5252 : : /* Re-enable ACS_SV if it was previously enabled */
5253 [ # # ]: 0 : if (ctrl & PCI_ACS_SV)
5254 : 0 : pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5255 : :
5256 : 0 : return found;
5257 : : }
5258 : :
5259 : : /*
5260 : : * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5261 : : * NT endpoints via the internal switch fabric. These IDs replace the
5262 : : * originating requestor ID TLPs which access host memory on peer NTB
5263 : : * ports. Therefore, all proxy IDs must be aliased to the NTB device
5264 : : * to permit access when the IOMMU is turned on.
5265 : : */
5266 : 0 : static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5267 : : {
5268 : 0 : void __iomem *mmio;
5269 : 0 : struct ntb_info_regs __iomem *mmio_ntb;
5270 : 0 : struct ntb_ctrl_regs __iomem *mmio_ctrl;
5271 : 0 : u64 partition_map;
5272 : 0 : u8 partition;
5273 : 0 : int pp;
5274 : :
5275 [ # # ]: 0 : if (pci_enable_device(pdev)) {
5276 : 0 : pci_err(pdev, "Cannot enable Switchtec device\n");
5277 : 0 : return;
5278 : : }
5279 : :
5280 : 0 : mmio = pci_iomap(pdev, 0, 0);
5281 [ # # ]: 0 : if (mmio == NULL) {
5282 : 0 : pci_disable_device(pdev);
5283 : 0 : pci_err(pdev, "Cannot iomap Switchtec device\n");
5284 : 0 : return;
5285 : : }
5286 : :
5287 : 0 : pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5288 : :
5289 : 0 : mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5290 : 0 : mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5291 : :
5292 : 0 : partition = ioread8(&mmio_ntb->partition_id);
5293 : :
5294 : 0 : partition_map = ioread32(&mmio_ntb->ep_map);
5295 : 0 : partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5296 : 0 : partition_map &= ~(1ULL << partition);
5297 : :
5298 [ # # ]: 0 : for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5299 : 0 : struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5300 : 0 : u32 table_sz = 0;
5301 : 0 : int te;
5302 : :
5303 [ # # ]: 0 : if (!(partition_map & (1ULL << pp)))
5304 : 0 : continue;
5305 : :
5306 : 0 : pci_dbg(pdev, "Processing partition %d\n", pp);
5307 : :
5308 : 0 : mmio_peer_ctrl = &mmio_ctrl[pp];
5309 : :
5310 : 0 : table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5311 [ # # ]: 0 : if (!table_sz) {
5312 : 0 : pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5313 : 0 : continue;
5314 : : }
5315 : :
5316 [ # # ]: 0 : if (table_sz > 512) {
5317 : 0 : pci_warn(pdev,
5318 : : "Invalid Switchtec partition %d table_sz %d\n",
5319 : : pp, table_sz);
5320 : 0 : continue;
5321 : : }
5322 : :
5323 [ # # ]: 0 : for (te = 0; te < table_sz; te++) {
5324 : 0 : u32 rid_entry;
5325 : 0 : u8 devfn;
5326 : :
5327 : 0 : rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5328 : 0 : devfn = (rid_entry >> 1) & 0xFF;
5329 : 0 : pci_dbg(pdev,
5330 : : "Aliasing Partition %d Proxy ID %02x.%d\n",
5331 : : pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5332 : 0 : pci_add_dma_alias(pdev, devfn, 1);
5333 : : }
5334 : : }
5335 : :
5336 : 0 : pci_iounmap(pdev, mmio);
5337 : 0 : pci_disable_device(pdev);
5338 : : }
5339 : : #define SWITCHTEC_QUIRK(vid) \
5340 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5341 : : PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5342 : :
5343 : : SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5344 : : SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5345 : : SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5346 : : SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5347 : : SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5348 : : SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5349 : : SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5350 : : SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5351 : : SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5352 : : SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5353 : : SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5354 : : SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5355 : : SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5356 : : SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5357 : : SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5358 : : SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5359 : : SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5360 : : SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5361 : : SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5362 : : SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5363 : : SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5364 : : SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5365 : : SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5366 : : SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5367 : : SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5368 : : SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5369 : : SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5370 : : SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5371 : : SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5372 : : SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5373 : : SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5374 : : SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5375 : : SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5376 : : SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5377 : : SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5378 : : SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5379 : : SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5380 : : SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5381 : : SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5382 : : SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5383 : : SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5384 : : SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5385 : : SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5386 : : SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5387 : : SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5388 : : SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5389 : : SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5390 : : SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5391 : :
5392 : : /*
5393 : : * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5394 : : * These IDs are used to forward responses to the originator on the other
5395 : : * side of the NTB. Alias all possible IDs to the NTB to permit access when
5396 : : * the IOMMU is turned on.
5397 : : */
5398 : 0 : static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5399 : : {
5400 : 0 : pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5401 : : /* PLX NTB may use all 256 devfns */
5402 : 0 : pci_add_dma_alias(pdev, 0, 256);
5403 : 0 : }
5404 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5405 : : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5406 : :
5407 : : /*
5408 : : * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5409 : : * not always reset the secondary Nvidia GPU between reboots if the system
5410 : : * is configured to use Hybrid Graphics mode. This results in the GPU
5411 : : * being left in whatever state it was in during the *previous* boot, which
5412 : : * causes spurious interrupts from the GPU, which in turn causes us to
5413 : : * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5414 : : * this also completely breaks nouveau.
5415 : : *
5416 : : * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5417 : : * clean state and fixes all these issues.
5418 : : *
5419 : : * When the machine is configured in Dedicated display mode, the issue
5420 : : * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5421 : : * mode, so we can detect that and avoid resetting it.
5422 : : */
5423 : 0 : static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5424 : : {
5425 : 0 : void __iomem *map;
5426 : 0 : int ret;
5427 : :
5428 [ # # ]: 0 : if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5429 : 0 : pdev->subsystem_device != 0x222e ||
5430 [ # # ]: 0 : !pdev->reset_fn)
5431 : : return;
5432 : :
5433 [ # # ]: 0 : if (pci_enable_device_mem(pdev))
5434 : : return;
5435 : :
5436 : : /*
5437 : : * Based on nvkm_device_ctor() in
5438 : : * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5439 : : */
5440 : 0 : map = pci_iomap(pdev, 0, 0x23000);
5441 [ # # ]: 0 : if (!map) {
5442 : 0 : pci_err(pdev, "Can't map MMIO space\n");
5443 : 0 : goto out_disable;
5444 : : }
5445 : :
5446 : : /*
5447 : : * Make sure the GPU looks like it's been POSTed before resetting
5448 : : * it.
5449 : : */
5450 [ # # ]: 0 : if (ioread32(map + 0x2240c) & 0x2) {
5451 : 0 : pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5452 : 0 : ret = pci_reset_bus(pdev);
5453 [ # # ]: 0 : if (ret < 0)
5454 : 0 : pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5455 : : }
5456 : :
5457 : 0 : iounmap(map);
5458 : 0 : out_disable:
5459 : 0 : pci_disable_device(pdev);
5460 : : }
5461 : : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5462 : : PCI_CLASS_DISPLAY_VGA, 8,
5463 : : quirk_reset_lenovo_thinkpad_p50_nvgpu);
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