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1 : : /*
2 : : * Copyright © 2008-2015 Intel Corporation
3 : : *
4 : : * Permission is hereby granted, free of charge, to any person obtaining a
5 : : * copy of this software and associated documentation files (the "Software"),
6 : : * to deal in the Software without restriction, including without limitation
7 : : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : : * and/or sell copies of the Software, and to permit persons to whom the
9 : : * Software is furnished to do so, subject to the following conditions:
10 : : *
11 : : * The above copyright notice and this permission notice (including the next
12 : : * paragraph) shall be included in all copies or substantial portions of the
13 : : * Software.
14 : : *
15 : : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 : : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 : : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 : : * IN THE SOFTWARE.
22 : : */
23 : :
24 : : #include "intel_display_types.h"
25 : : #include "intel_dp.h"
26 : : #include "intel_dp_link_training.h"
27 : :
28 : : static void
29 : 0 : intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
30 : : {
31 : :
32 : 0 : DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
33 : : link_status[0], link_status[1], link_status[2],
34 : : link_status[3], link_status[4], link_status[5]);
35 : 0 : }
36 : :
37 : : static void
38 : 0 : intel_get_adjust_train(struct intel_dp *intel_dp,
39 : : const u8 link_status[DP_LINK_STATUS_SIZE])
40 : : {
41 : 0 : u8 v = 0;
42 : 0 : u8 p = 0;
43 : 0 : int lane;
44 : 0 : u8 voltage_max;
45 : 0 : u8 preemph_max;
46 : :
47 [ # # ]: 0 : for (lane = 0; lane < intel_dp->lane_count; lane++) {
48 : 0 : u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
49 : 0 : u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
50 : :
51 : 0 : if (this_v > v)
52 : : v = this_v;
53 : 0 : if (this_p > p)
54 : : p = this_p;
55 : : }
56 : :
57 : 0 : voltage_max = intel_dp_voltage_max(intel_dp);
58 [ # # ]: 0 : if (v >= voltage_max)
59 : 0 : v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
60 : :
61 : 0 : preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
62 [ # # ]: 0 : if (p >= preemph_max)
63 : 0 : p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
64 : :
65 [ # # ]: 0 : for (lane = 0; lane < 4; lane++)
66 : 0 : intel_dp->train_set[lane] = v | p;
67 : 0 : }
68 : :
69 : : static bool
70 : 0 : intel_dp_set_link_train(struct intel_dp *intel_dp,
71 : : u8 dp_train_pat)
72 : : {
73 : 0 : u8 buf[sizeof(intel_dp->train_set) + 1];
74 : 0 : int ret, len;
75 : :
76 : 0 : intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
77 : :
78 : 0 : buf[0] = dp_train_pat;
79 [ # # ]: 0 : if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
80 : : DP_TRAINING_PATTERN_DISABLE) {
81 : : /* don't write DP_TRAINING_LANEx_SET on disable */
82 : : len = 1;
83 : : } else {
84 : : /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
85 : 0 : memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
86 : 0 : len = intel_dp->lane_count + 1;
87 : : }
88 : :
89 : 0 : ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
90 : : buf, len);
91 : :
92 : 0 : return ret == len;
93 : : }
94 : :
95 : : static bool
96 : 0 : intel_dp_reset_link_train(struct intel_dp *intel_dp,
97 : : u8 dp_train_pat)
98 : : {
99 : 0 : memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
100 : 0 : intel_dp_set_signal_levels(intel_dp);
101 : 0 : return intel_dp_set_link_train(intel_dp, dp_train_pat);
102 : : }
103 : :
104 : : static bool
105 : 0 : intel_dp_update_link_train(struct intel_dp *intel_dp)
106 : : {
107 : 0 : int ret;
108 : :
109 : 0 : intel_dp_set_signal_levels(intel_dp);
110 : :
111 : 0 : ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
112 : 0 : intel_dp->train_set, intel_dp->lane_count);
113 : :
114 : 0 : return ret == intel_dp->lane_count;
115 : : }
116 : :
117 : 0 : static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
118 : : {
119 : 0 : int lane;
120 : :
121 [ # # ]: 0 : for (lane = 0; lane < intel_dp->lane_count; lane++)
122 [ # # ]: 0 : if ((intel_dp->train_set[lane] &
123 : : DP_TRAIN_MAX_SWING_REACHED) == 0)
124 : : return false;
125 : :
126 : : return true;
127 : : }
128 : :
129 : : /* Enable corresponding port and start training pattern 1 */
130 : : static bool
131 : 0 : intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
132 : : {
133 : 0 : u8 voltage;
134 : 0 : int voltage_tries, cr_tries, max_cr_tries;
135 : 0 : bool max_vswing_reached = false;
136 : 0 : u8 link_config[2];
137 : 0 : u8 link_bw, rate_select;
138 : :
139 [ # # ]: 0 : if (intel_dp->prepare_link_retrain)
140 : 0 : intel_dp->prepare_link_retrain(intel_dp);
141 : :
142 : 0 : intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
143 : : &link_bw, &rate_select);
144 : :
145 [ # # ]: 0 : if (link_bw)
146 : 0 : DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw);
147 : : else
148 : 0 : DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select);
149 : :
150 : : /* Write the link configuration data */
151 : 0 : link_config[0] = link_bw;
152 : 0 : link_config[1] = intel_dp->lane_count;
153 [ # # # # ]: 0 : if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
154 : 0 : link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
155 : 0 : drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
156 : :
157 : : /* eDP 1.4 rate select method. */
158 [ # # ]: 0 : if (!link_bw)
159 : 0 : drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
160 : : &rate_select, 1);
161 : :
162 : 0 : link_config[0] = 0;
163 : 0 : link_config[1] = DP_SET_ANSI_8B10B;
164 : 0 : drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
165 : :
166 : 0 : intel_dp->DP |= DP_PORT_EN;
167 : :
168 : : /* clock recovery */
169 [ # # ]: 0 : if (!intel_dp_reset_link_train(intel_dp,
170 : : DP_TRAINING_PATTERN_1 |
171 : : DP_LINK_SCRAMBLING_DISABLE)) {
172 : 0 : DRM_ERROR("failed to enable link training\n");
173 : 0 : return false;
174 : : }
175 : :
176 : : /*
177 : : * The DP 1.4 spec defines the max clock recovery retries value
178 : : * as 10 but for pre-DP 1.4 devices we set a very tolerant
179 : : * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
180 : : * x 5 identical voltage retries). Since the previous specs didn't
181 : : * define a limit and created the possibility of an infinite loop
182 : : * we want to prevent any sync from triggering that corner case.
183 : : */
184 [ # # ]: 0 : if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
185 : : max_cr_tries = 10;
186 : : else
187 : 0 : max_cr_tries = 80;
188 : :
189 : 0 : voltage_tries = 1;
190 [ # # ]: 0 : for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
191 : 0 : u8 link_status[DP_LINK_STATUS_SIZE];
192 : :
193 : 0 : drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
194 : :
195 [ # # ]: 0 : if (!intel_dp_get_link_status(intel_dp, link_status)) {
196 : 0 : DRM_ERROR("failed to get link status\n");
197 : 0 : return false;
198 : : }
199 : :
200 [ # # ]: 0 : if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
201 : 0 : DRM_DEBUG_KMS("clock recovery OK\n");
202 : 0 : return true;
203 : : }
204 : :
205 [ # # ]: 0 : if (voltage_tries == 5) {
206 : 0 : DRM_DEBUG_KMS("Same voltage tried 5 times\n");
207 : 0 : return false;
208 : : }
209 : :
210 [ # # ]: 0 : if (max_vswing_reached) {
211 : 0 : DRM_DEBUG_KMS("Max Voltage Swing reached\n");
212 : 0 : return false;
213 : : }
214 : :
215 : 0 : voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
216 : :
217 : : /* Update training set as requested by target */
218 : 0 : intel_get_adjust_train(intel_dp, link_status);
219 [ # # ]: 0 : if (!intel_dp_update_link_train(intel_dp)) {
220 : 0 : DRM_ERROR("failed to update link training\n");
221 : 0 : return false;
222 : : }
223 : :
224 [ # # ]: 0 : if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
225 : : voltage)
226 : 0 : ++voltage_tries;
227 : : else
228 : : voltage_tries = 1;
229 : :
230 [ # # ]: 0 : if (intel_dp_link_max_vswing_reached(intel_dp))
231 : 0 : max_vswing_reached = true;
232 : :
233 : : }
234 : 0 : DRM_ERROR("Failed clock recovery %d times, giving up!\n", max_cr_tries);
235 : 0 : return false;
236 : : }
237 : :
238 : : /*
239 : : * Pick training pattern for channel equalization. Training pattern 4 for HBR3
240 : : * or for 1.4 devices that support it, training Pattern 3 for HBR2
241 : : * or 1.2 devices that support it, Training Pattern 2 otherwise.
242 : : */
243 : 0 : static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
244 : : {
245 : 0 : bool source_tps3, sink_tps3, source_tps4, sink_tps4;
246 : :
247 : : /*
248 : : * Intel platforms that support HBR3 also support TPS4. It is mandatory
249 : : * for all downstream devices that support HBR3. There are no known eDP
250 : : * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
251 : : * specification.
252 : : */
253 : 0 : source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
254 [ # # ]: 0 : sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
255 [ # # ]: 0 : if (source_tps4 && sink_tps4) {
256 : : return DP_TRAINING_PATTERN_4;
257 [ # # ]: 0 : } else if (intel_dp->link_rate == 810000) {
258 [ # # ]: 0 : if (!source_tps4)
259 : 0 : DRM_DEBUG_KMS("8.1 Gbps link rate without source HBR3/TPS4 support\n");
260 [ # # ]: 0 : if (!sink_tps4)
261 : 0 : DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n");
262 : : }
263 : : /*
264 : : * Intel platforms that support HBR2 also support TPS3. TPS3 support is
265 : : * also mandatory for downstream devices that support HBR2. However, not
266 : : * all sinks follow the spec.
267 : : */
268 : 0 : source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
269 [ # # ]: 0 : sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
270 [ # # ]: 0 : if (source_tps3 && sink_tps3) {
271 : : return DP_TRAINING_PATTERN_3;
272 [ # # ]: 0 : } else if (intel_dp->link_rate >= 540000) {
273 [ # # ]: 0 : if (!source_tps3)
274 : 0 : DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
275 [ # # ]: 0 : if (!sink_tps3)
276 : 0 : DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
277 : : }
278 : :
279 : : return DP_TRAINING_PATTERN_2;
280 : : }
281 : :
282 : : static bool
283 : 0 : intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
284 : : {
285 : 0 : int tries;
286 : 0 : u32 training_pattern;
287 : 0 : u8 link_status[DP_LINK_STATUS_SIZE];
288 : 0 : bool channel_eq = false;
289 : :
290 : 0 : training_pattern = intel_dp_training_pattern(intel_dp);
291 : : /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
292 [ # # ]: 0 : if (training_pattern != DP_TRAINING_PATTERN_4)
293 : 0 : training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
294 : :
295 : : /* channel equalization */
296 [ # # ]: 0 : if (!intel_dp_set_link_train(intel_dp,
297 : : training_pattern)) {
298 : 0 : DRM_ERROR("failed to start channel equalization\n");
299 : 0 : return false;
300 : : }
301 : :
302 [ # # ]: 0 : for (tries = 0; tries < 5; tries++) {
303 : :
304 : 0 : drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
305 [ # # ]: 0 : if (!intel_dp_get_link_status(intel_dp, link_status)) {
306 : 0 : DRM_ERROR("failed to get link status\n");
307 : 0 : break;
308 : : }
309 : :
310 : : /* Make sure clock is still ok */
311 [ # # ]: 0 : if (!drm_dp_clock_recovery_ok(link_status,
312 : 0 : intel_dp->lane_count)) {
313 : 0 : intel_dp_dump_link_status(link_status);
314 : 0 : DRM_DEBUG_KMS("Clock recovery check failed, cannot "
315 : : "continue channel equalization\n");
316 : 0 : break;
317 : : }
318 : :
319 [ # # ]: 0 : if (drm_dp_channel_eq_ok(link_status,
320 : 0 : intel_dp->lane_count)) {
321 : 0 : channel_eq = true;
322 : 0 : DRM_DEBUG_KMS("Channel EQ done. DP Training "
323 : : "successful\n");
324 : 0 : break;
325 : : }
326 : :
327 : : /* Update training set as requested by target */
328 : 0 : intel_get_adjust_train(intel_dp, link_status);
329 [ # # ]: 0 : if (!intel_dp_update_link_train(intel_dp)) {
330 : 0 : DRM_ERROR("failed to update link training\n");
331 : 0 : break;
332 : : }
333 : : }
334 : :
335 : : /* Try 5 times, else fail and try at lower BW */
336 [ # # ]: 0 : if (tries == 5) {
337 : 0 : intel_dp_dump_link_status(link_status);
338 : 0 : DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
339 : : }
340 : :
341 : 0 : intel_dp_set_idle_link_train(intel_dp);
342 : :
343 : 0 : return channel_eq;
344 : :
345 : : }
346 : :
347 : 0 : void intel_dp_stop_link_train(struct intel_dp *intel_dp)
348 : : {
349 : 0 : intel_dp->link_trained = true;
350 : :
351 : 0 : intel_dp_set_link_train(intel_dp,
352 : : DP_TRAINING_PATTERN_DISABLE);
353 : 0 : }
354 : :
355 : : void
356 : 0 : intel_dp_start_link_train(struct intel_dp *intel_dp)
357 : : {
358 : 0 : struct intel_connector *intel_connector = intel_dp->attached_connector;
359 : :
360 [ # # ]: 0 : if (!intel_dp_link_training_clock_recovery(intel_dp))
361 : 0 : goto failure_handling;
362 [ # # ]: 0 : if (!intel_dp_link_training_channel_equalization(intel_dp))
363 : 0 : goto failure_handling;
364 : :
365 : 0 : DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
366 : : intel_connector->base.base.id,
367 : : intel_connector->base.name,
368 : : intel_dp->link_rate, intel_dp->lane_count);
369 : 0 : return;
370 : :
371 : 0 : failure_handling:
372 : 0 : DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
373 : : intel_connector->base.base.id,
374 : : intel_connector->base.name,
375 : : intel_dp->link_rate, intel_dp->lane_count);
376 [ # # ]: 0 : if (!intel_dp_get_link_train_fallback_values(intel_dp,
377 : : intel_dp->link_rate,
378 : 0 : intel_dp->lane_count))
379 : : /* Schedule a Hotplug Uevent to userspace to start modeset */
380 : 0 : schedule_work(&intel_connector->modeset_retry_work);
381 : : return;
382 : : }
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