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1 : : /* SPDX-License-Identifier: GPL-2.0 */
2 : : /*
3 : : * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 : : * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 : : */
6 : : #ifndef __LINUX_CLK_PROVIDER_H
7 : : #define __LINUX_CLK_PROVIDER_H
8 : :
9 : : #include <linux/of.h>
10 : : #include <linux/of_clk.h>
11 : :
12 : : /*
13 : : * flags used across common struct clk. these flags should only affect the
14 : : * top-level framework. custom flags for dealing with hardware specifics
15 : : * belong in struct clk_foo
16 : : *
17 : : * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 : : */
19 : : #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 : : #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 : : #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 : : #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 : : /* unused */
24 : : /* unused */
25 : : #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 : : #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 : : #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 : : #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 : : #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 : : #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 : : /* parents need enable during gate/ungate, set rate and re-parent */
32 : : #define CLK_OPS_PARENT_ENABLE BIT(12)
33 : : /* duty cycle call may be forwarded to the parent clock */
34 : : #define CLK_DUTY_CYCLE_PARENT BIT(13)
35 : :
36 : : struct clk;
37 : : struct clk_hw;
38 : : struct clk_core;
39 : : struct dentry;
40 : :
41 : : /**
42 : : * struct clk_rate_request - Structure encoding the clk constraints that
43 : : * a clock user might require.
44 : : *
45 : : * @rate: Requested clock rate. This field will be adjusted by
46 : : * clock drivers according to hardware capabilities.
47 : : * @min_rate: Minimum rate imposed by clk users.
48 : : * @max_rate: Maximum rate imposed by clk users.
49 : : * @best_parent_rate: The best parent rate a parent can provide to fulfill the
50 : : * requested constraints.
51 : : * @best_parent_hw: The most appropriate parent clock that fulfills the
52 : : * requested constraints.
53 : : *
54 : : */
55 : : struct clk_rate_request {
56 : : unsigned long rate;
57 : : unsigned long min_rate;
58 : : unsigned long max_rate;
59 : : unsigned long best_parent_rate;
60 : : struct clk_hw *best_parent_hw;
61 : : };
62 : :
63 : : /**
64 : : * struct clk_duty - Struture encoding the duty cycle ratio of a clock
65 : : *
66 : : * @num: Numerator of the duty cycle ratio
67 : : * @den: Denominator of the duty cycle ratio
68 : : */
69 : : struct clk_duty {
70 : : unsigned int num;
71 : : unsigned int den;
72 : : };
73 : :
74 : : /**
75 : : * struct clk_ops - Callback operations for hardware clocks; these are to
76 : : * be provided by the clock implementation, and will be called by drivers
77 : : * through the clk_* api.
78 : : *
79 : : * @prepare: Prepare the clock for enabling. This must not return until
80 : : * the clock is fully prepared, and it's safe to call clk_enable.
81 : : * This callback is intended to allow clock implementations to
82 : : * do any initialisation that may sleep. Called with
83 : : * prepare_lock held.
84 : : *
85 : : * @unprepare: Release the clock from its prepared state. This will typically
86 : : * undo any work done in the @prepare callback. Called with
87 : : * prepare_lock held.
88 : : *
89 : : * @is_prepared: Queries the hardware to determine if the clock is prepared.
90 : : * This function is allowed to sleep. Optional, if this op is not
91 : : * set then the prepare count will be used.
92 : : *
93 : : * @unprepare_unused: Unprepare the clock atomically. Only called from
94 : : * clk_disable_unused for prepare clocks with special needs.
95 : : * Called with prepare mutex held. This function may sleep.
96 : : *
97 : : * @enable: Enable the clock atomically. This must not return until the
98 : : * clock is generating a valid clock signal, usable by consumer
99 : : * devices. Called with enable_lock held. This function must not
100 : : * sleep.
101 : : *
102 : : * @disable: Disable the clock atomically. Called with enable_lock held.
103 : : * This function must not sleep.
104 : : *
105 : : * @is_enabled: Queries the hardware to determine if the clock is enabled.
106 : : * This function must not sleep. Optional, if this op is not
107 : : * set then the enable count will be used.
108 : : *
109 : : * @disable_unused: Disable the clock atomically. Only called from
110 : : * clk_disable_unused for gate clocks with special needs.
111 : : * Called with enable_lock held. This function must not
112 : : * sleep.
113 : : *
114 : : * @save_context: Save the context of the clock in prepration for poweroff.
115 : : *
116 : : * @restore_context: Restore the context of the clock after a restoration
117 : : * of power.
118 : : *
119 : : * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
120 : : * parent rate is an input parameter. It is up to the caller to
121 : : * ensure that the prepare_mutex is held across this call.
122 : : * Returns the calculated rate. Optional, but recommended - if
123 : : * this op is not set then clock rate will be initialized to 0.
124 : : *
125 : : * @round_rate: Given a target rate as input, returns the closest rate actually
126 : : * supported by the clock. The parent rate is an input/output
127 : : * parameter.
128 : : *
129 : : * @determine_rate: Given a target rate as input, returns the closest rate
130 : : * actually supported by the clock, and optionally the parent clock
131 : : * that should be used to provide the clock rate.
132 : : *
133 : : * @set_parent: Change the input source of this clock; for clocks with multiple
134 : : * possible parents specify a new parent by passing in the index
135 : : * as a u8 corresponding to the parent in either the .parent_names
136 : : * or .parents arrays. This function in affect translates an
137 : : * array index into the value programmed into the hardware.
138 : : * Returns 0 on success, -EERROR otherwise.
139 : : *
140 : : * @get_parent: Queries the hardware to determine the parent of a clock. The
141 : : * return value is a u8 which specifies the index corresponding to
142 : : * the parent clock. This index can be applied to either the
143 : : * .parent_names or .parents arrays. In short, this function
144 : : * translates the parent value read from hardware into an array
145 : : * index. Currently only called when the clock is initialized by
146 : : * __clk_init. This callback is mandatory for clocks with
147 : : * multiple parents. It is optional (and unnecessary) for clocks
148 : : * with 0 or 1 parents.
149 : : *
150 : : * @set_rate: Change the rate of this clock. The requested rate is specified
151 : : * by the second argument, which should typically be the return
152 : : * of .round_rate call. The third argument gives the parent rate
153 : : * which is likely helpful for most .set_rate implementation.
154 : : * Returns 0 on success, -EERROR otherwise.
155 : : *
156 : : * @set_rate_and_parent: Change the rate and the parent of this clock. The
157 : : * requested rate is specified by the second argument, which
158 : : * should typically be the return of .round_rate call. The
159 : : * third argument gives the parent rate which is likely helpful
160 : : * for most .set_rate_and_parent implementation. The fourth
161 : : * argument gives the parent index. This callback is optional (and
162 : : * unnecessary) for clocks with 0 or 1 parents as well as
163 : : * for clocks that can tolerate switching the rate and the parent
164 : : * separately via calls to .set_parent and .set_rate.
165 : : * Returns 0 on success, -EERROR otherwise.
166 : : *
167 : : * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
168 : : * is expressed in ppb (parts per billion). The parent accuracy is
169 : : * an input parameter.
170 : : * Returns the calculated accuracy. Optional - if this op is not
171 : : * set then clock accuracy will be initialized to parent accuracy
172 : : * or 0 (perfect clock) if clock has no parent.
173 : : *
174 : : * @get_phase: Queries the hardware to get the current phase of a clock.
175 : : * Returned values are 0-359 degrees on success, negative
176 : : * error codes on failure.
177 : : *
178 : : * @set_phase: Shift the phase this clock signal in degrees specified
179 : : * by the second argument. Valid values for degrees are
180 : : * 0-359. Return 0 on success, otherwise -EERROR.
181 : : *
182 : : * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
183 : : * of a clock. Returned values denominator cannot be 0 and must be
184 : : * superior or equal to the numerator.
185 : : *
186 : : * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
187 : : * the numerator (2nd argurment) and denominator (3rd argument).
188 : : * Argument must be a valid ratio (denominator > 0
189 : : * and >= numerator) Return 0 on success, otherwise -EERROR.
190 : : *
191 : : * @init: Perform platform-specific initialization magic.
192 : : * This is not not used by any of the basic clock types.
193 : : * This callback exist for HW which needs to perform some
194 : : * initialisation magic for CCF to get an accurate view of the
195 : : * clock. It may also be used dynamic resource allocation is
196 : : * required. It shall not used to deal with clock parameters,
197 : : * such as rate or parents.
198 : : * Returns 0 on success, -EERROR otherwise.
199 : : *
200 : : * @terminate: Free any resource allocated by init.
201 : : *
202 : : * @debug_init: Set up type-specific debugfs entries for this clock. This
203 : : * is called once, after the debugfs directory entry for this
204 : : * clock has been created. The dentry pointer representing that
205 : : * directory is provided as an argument. Called with
206 : : * prepare_lock held. Returns 0 on success, -EERROR otherwise.
207 : : *
208 : : *
209 : : * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
210 : : * implementations to split any work between atomic (enable) and sleepable
211 : : * (prepare) contexts. If enabling a clock requires code that might sleep,
212 : : * this must be done in clk_prepare. Clock enable code that will never be
213 : : * called in a sleepable context may be implemented in clk_enable.
214 : : *
215 : : * Typically, drivers will call clk_prepare when a clock may be needed later
216 : : * (eg. when a device is opened), and clk_enable when the clock is actually
217 : : * required (eg. from an interrupt). Note that clk_prepare MUST have been
218 : : * called before clk_enable.
219 : : */
220 : : struct clk_ops {
221 : : int (*prepare)(struct clk_hw *hw);
222 : : void (*unprepare)(struct clk_hw *hw);
223 : : int (*is_prepared)(struct clk_hw *hw);
224 : : void (*unprepare_unused)(struct clk_hw *hw);
225 : : int (*enable)(struct clk_hw *hw);
226 : : void (*disable)(struct clk_hw *hw);
227 : : int (*is_enabled)(struct clk_hw *hw);
228 : : void (*disable_unused)(struct clk_hw *hw);
229 : : int (*save_context)(struct clk_hw *hw);
230 : : void (*restore_context)(struct clk_hw *hw);
231 : : unsigned long (*recalc_rate)(struct clk_hw *hw,
232 : : unsigned long parent_rate);
233 : : long (*round_rate)(struct clk_hw *hw, unsigned long rate,
234 : : unsigned long *parent_rate);
235 : : int (*determine_rate)(struct clk_hw *hw,
236 : : struct clk_rate_request *req);
237 : : int (*set_parent)(struct clk_hw *hw, u8 index);
238 : : u8 (*get_parent)(struct clk_hw *hw);
239 : : int (*set_rate)(struct clk_hw *hw, unsigned long rate,
240 : : unsigned long parent_rate);
241 : : int (*set_rate_and_parent)(struct clk_hw *hw,
242 : : unsigned long rate,
243 : : unsigned long parent_rate, u8 index);
244 : : unsigned long (*recalc_accuracy)(struct clk_hw *hw,
245 : : unsigned long parent_accuracy);
246 : : int (*get_phase)(struct clk_hw *hw);
247 : : int (*set_phase)(struct clk_hw *hw, int degrees);
248 : : int (*get_duty_cycle)(struct clk_hw *hw,
249 : : struct clk_duty *duty);
250 : : int (*set_duty_cycle)(struct clk_hw *hw,
251 : : struct clk_duty *duty);
252 : : int (*init)(struct clk_hw *hw);
253 : : void (*terminate)(struct clk_hw *hw);
254 : : void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
255 : : };
256 : :
257 : : /**
258 : : * struct clk_parent_data - clk parent information
259 : : * @hw: parent clk_hw pointer (used for clk providers with internal clks)
260 : : * @fw_name: parent name local to provider registering clk
261 : : * @name: globally unique parent name (used as a fallback)
262 : : * @index: parent index local to provider registering clk (if @fw_name absent)
263 : : */
264 : : struct clk_parent_data {
265 : : const struct clk_hw *hw;
266 : : const char *fw_name;
267 : : const char *name;
268 : : int index;
269 : : };
270 : :
271 : : /**
272 : : * struct clk_init_data - holds init data that's common to all clocks and is
273 : : * shared between the clock provider and the common clock framework.
274 : : *
275 : : * @name: clock name
276 : : * @ops: operations this clock supports
277 : : * @parent_names: array of string names for all possible parents
278 : : * @parent_data: array of parent data for all possible parents (when some
279 : : * parents are external to the clk controller)
280 : : * @parent_hws: array of pointers to all possible parents (when all parents
281 : : * are internal to the clk controller)
282 : : * @num_parents: number of possible parents
283 : : * @flags: framework-level hints and quirks
284 : : */
285 : : struct clk_init_data {
286 : : const char *name;
287 : : const struct clk_ops *ops;
288 : : /* Only one of the following three should be assigned */
289 : : const char * const *parent_names;
290 : : const struct clk_parent_data *parent_data;
291 : : const struct clk_hw **parent_hws;
292 : : u8 num_parents;
293 : : unsigned long flags;
294 : : };
295 : :
296 : : /**
297 : : * struct clk_hw - handle for traversing from a struct clk to its corresponding
298 : : * hardware-specific structure. struct clk_hw should be declared within struct
299 : : * clk_foo and then referenced by the struct clk instance that uses struct
300 : : * clk_foo's clk_ops
301 : : *
302 : : * @core: pointer to the struct clk_core instance that points back to this
303 : : * struct clk_hw instance
304 : : *
305 : : * @clk: pointer to the per-user struct clk instance that can be used to call
306 : : * into the clk API
307 : : *
308 : : * @init: pointer to struct clk_init_data that contains the init data shared
309 : : * with the common clock framework. This pointer will be set to NULL once
310 : : * a clk_register() variant is called on this clk_hw pointer.
311 : : */
312 : : struct clk_hw {
313 : : struct clk_core *core;
314 : : struct clk *clk;
315 : : const struct clk_init_data *init;
316 : : };
317 : :
318 : : /*
319 : : * DOC: Basic clock implementations common to many platforms
320 : : *
321 : : * Each basic clock hardware type is comprised of a structure describing the
322 : : * clock hardware, implementations of the relevant callbacks in struct clk_ops,
323 : : * unique flags for that hardware type, a registration function and an
324 : : * alternative macro for static initialization
325 : : */
326 : :
327 : : /**
328 : : * struct clk_fixed_rate - fixed-rate clock
329 : : * @hw: handle between common and hardware-specific interfaces
330 : : * @fixed_rate: constant frequency of clock
331 : : * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
332 : : * @flags: hardware specific flags
333 : : *
334 : : * Flags:
335 : : * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
336 : : * instead of what's set in @fixed_accuracy.
337 : : */
338 : : struct clk_fixed_rate {
339 : : struct clk_hw hw;
340 : : unsigned long fixed_rate;
341 : : unsigned long fixed_accuracy;
342 : : unsigned long flags;
343 : : };
344 : :
345 : : #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
346 : :
347 : : extern const struct clk_ops clk_fixed_rate_ops;
348 : : struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
349 : : struct device_node *np, const char *name,
350 : : const char *parent_name, const struct clk_hw *parent_hw,
351 : : const struct clk_parent_data *parent_data, unsigned long flags,
352 : : unsigned long fixed_rate, unsigned long fixed_accuracy,
353 : : unsigned long clk_fixed_flags);
354 : : struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
355 : : const char *parent_name, unsigned long flags,
356 : : unsigned long fixed_rate);
357 : : /**
358 : : * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
359 : : * framework
360 : : * @dev: device that is registering this clock
361 : : * @name: name of this clock
362 : : * @parent_name: name of clock's parent
363 : : * @flags: framework-specific flags
364 : : * @fixed_rate: non-adjustable clock rate
365 : : */
366 : : #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
367 : : __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
368 : : NULL, (flags), (fixed_rate), 0, 0)
369 : : /**
370 : : * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
371 : : * the clock framework
372 : : * @dev: device that is registering this clock
373 : : * @name: name of this clock
374 : : * @parent_hw: pointer to parent clk
375 : : * @flags: framework-specific flags
376 : : * @fixed_rate: non-adjustable clock rate
377 : : */
378 : : #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
379 : : fixed_rate) \
380 : : __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
381 : : NULL, (flags), (fixed_rate), 0, 0)
382 : : /**
383 : : * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
384 : : * the clock framework
385 : : * @dev: device that is registering this clock
386 : : * @name: name of this clock
387 : : * @parent_data: parent clk data
388 : : * @flags: framework-specific flags
389 : : * @fixed_rate: non-adjustable clock rate
390 : : */
391 : : #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
392 : : fixed_rate) \
393 : : __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
394 : : (parent_data), (flags), (fixed_rate), 0, \
395 : : 0)
396 : : /**
397 : : * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
398 : : * the clock framework
399 : : * @dev: device that is registering this clock
400 : : * @name: name of this clock
401 : : * @parent_name: name of clock's parent
402 : : * @flags: framework-specific flags
403 : : * @fixed_rate: non-adjustable clock rate
404 : : * @fixed_accuracy: non-adjustable clock accuracy
405 : : */
406 : : #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
407 : : flags, fixed_rate, \
408 : : fixed_accuracy) \
409 : : __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
410 : : NULL, NULL, (flags), (fixed_rate), \
411 : : (fixed_accuracy), 0)
412 : : /**
413 : : * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
414 : : * clock with the clock framework
415 : : * @dev: device that is registering this clock
416 : : * @name: name of this clock
417 : : * @parent_hw: pointer to parent clk
418 : : * @flags: framework-specific flags
419 : : * @fixed_rate: non-adjustable clock rate
420 : : * @fixed_accuracy: non-adjustable clock accuracy
421 : : */
422 : : #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
423 : : parent_hw, flags, fixed_rate, fixed_accuracy) \
424 : : __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
425 : : NULL, NULL, (flags), (fixed_rate), \
426 : : (fixed_accuracy), 0)
427 : : /**
428 : : * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
429 : : * clock with the clock framework
430 : : * @dev: device that is registering this clock
431 : : * @name: name of this clock
432 : : * @parent_name: name of clock's parent
433 : : * @flags: framework-specific flags
434 : : * @fixed_rate: non-adjustable clock rate
435 : : * @fixed_accuracy: non-adjustable clock accuracy
436 : : */
437 : : #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
438 : : parent_data, flags, fixed_rate, fixed_accuracy) \
439 : : __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
440 : : (parent_data), NULL, (flags), \
441 : : (fixed_rate), (fixed_accuracy), 0)
442 : :
443 : : void clk_unregister_fixed_rate(struct clk *clk);
444 : : void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
445 : :
446 : : void of_fixed_clk_setup(struct device_node *np);
447 : :
448 : : /**
449 : : * struct clk_gate - gating clock
450 : : *
451 : : * @hw: handle between common and hardware-specific interfaces
452 : : * @reg: register controlling gate
453 : : * @bit_idx: single bit controlling gate
454 : : * @flags: hardware-specific flags
455 : : * @lock: register lock
456 : : *
457 : : * Clock which can gate its output. Implements .enable & .disable
458 : : *
459 : : * Flags:
460 : : * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
461 : : * enable the clock. Setting this flag does the opposite: setting the bit
462 : : * disable the clock and clearing it enables the clock
463 : : * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
464 : : * of this register, and mask of gate bits are in higher 16-bit of this
465 : : * register. While setting the gate bits, higher 16-bit should also be
466 : : * updated to indicate changing gate bits.
467 : : * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
468 : : * the gate register. Setting this flag makes the register accesses big
469 : : * endian.
470 : : */
471 : : struct clk_gate {
472 : : struct clk_hw hw;
473 : : void __iomem *reg;
474 : : u8 bit_idx;
475 : : u8 flags;
476 : : spinlock_t *lock;
477 : : };
478 : :
479 : : #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
480 : :
481 : : #define CLK_GATE_SET_TO_DISABLE BIT(0)
482 : : #define CLK_GATE_HIWORD_MASK BIT(1)
483 : : #define CLK_GATE_BIG_ENDIAN BIT(2)
484 : :
485 : : extern const struct clk_ops clk_gate_ops;
486 : : struct clk_hw *__clk_hw_register_gate(struct device *dev,
487 : : struct device_node *np, const char *name,
488 : : const char *parent_name, const struct clk_hw *parent_hw,
489 : : const struct clk_parent_data *parent_data,
490 : : unsigned long flags,
491 : : void __iomem *reg, u8 bit_idx,
492 : : u8 clk_gate_flags, spinlock_t *lock);
493 : : struct clk *clk_register_gate(struct device *dev, const char *name,
494 : : const char *parent_name, unsigned long flags,
495 : : void __iomem *reg, u8 bit_idx,
496 : : u8 clk_gate_flags, spinlock_t *lock);
497 : : /**
498 : : * clk_hw_register_gate - register a gate clock with the clock framework
499 : : * @dev: device that is registering this clock
500 : : * @name: name of this clock
501 : : * @parent_name: name of this clock's parent
502 : : * @flags: framework-specific flags for this clock
503 : : * @reg: register address to control gating of this clock
504 : : * @bit_idx: which bit in the register controls gating of this clock
505 : : * @clk_gate_flags: gate-specific flags for this clock
506 : : * @lock: shared register lock for this clock
507 : : */
508 : : #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
509 : : clk_gate_flags, lock) \
510 : : __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
511 : : NULL, (flags), (reg), (bit_idx), \
512 : : (clk_gate_flags), (lock))
513 : : /**
514 : : * clk_hw_register_gate_parent_hw - register a gate clock with the clock
515 : : * framework
516 : : * @dev: device that is registering this clock
517 : : * @name: name of this clock
518 : : * @parent_hw: pointer to parent clk
519 : : * @flags: framework-specific flags for this clock
520 : : * @reg: register address to control gating of this clock
521 : : * @bit_idx: which bit in the register controls gating of this clock
522 : : * @clk_gate_flags: gate-specific flags for this clock
523 : : * @lock: shared register lock for this clock
524 : : */
525 : : #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
526 : : bit_idx, clk_gate_flags, lock) \
527 : : __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
528 : : NULL, (flags), (reg), (bit_idx), \
529 : : (clk_gate_flags), (lock))
530 : : /**
531 : : * clk_hw_register_gate_parent_data - register a gate clock with the clock
532 : : * framework
533 : : * @dev: device that is registering this clock
534 : : * @name: name of this clock
535 : : * @parent_data: parent clk data
536 : : * @flags: framework-specific flags for this clock
537 : : * @reg: register address to control gating of this clock
538 : : * @bit_idx: which bit in the register controls gating of this clock
539 : : * @clk_gate_flags: gate-specific flags for this clock
540 : : * @lock: shared register lock for this clock
541 : : */
542 : : #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
543 : : bit_idx, clk_gate_flags, lock) \
544 : : __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
545 : : (flags), (reg), (bit_idx), \
546 : : (clk_gate_flags), (lock))
547 : : void clk_unregister_gate(struct clk *clk);
548 : : void clk_hw_unregister_gate(struct clk_hw *hw);
549 : : int clk_gate_is_enabled(struct clk_hw *hw);
550 : :
551 : : struct clk_div_table {
552 : : unsigned int val;
553 : : unsigned int div;
554 : : };
555 : :
556 : : /**
557 : : * struct clk_divider - adjustable divider clock
558 : : *
559 : : * @hw: handle between common and hardware-specific interfaces
560 : : * @reg: register containing the divider
561 : : * @shift: shift to the divider bit field
562 : : * @width: width of the divider bit field
563 : : * @table: array of value/divider pairs, last entry should have div = 0
564 : : * @lock: register lock
565 : : *
566 : : * Clock with an adjustable divider affecting its output frequency. Implements
567 : : * .recalc_rate, .set_rate and .round_rate
568 : : *
569 : : * Flags:
570 : : * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
571 : : * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
572 : : * the raw value read from the register, with the value of zero considered
573 : : * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
574 : : * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
575 : : * the hardware register
576 : : * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
577 : : * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
578 : : * Some hardware implementations gracefully handle this case and allow a
579 : : * zero divisor by not modifying their input clock
580 : : * (divide by one / bypass).
581 : : * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
582 : : * of this register, and mask of divider bits are in higher 16-bit of this
583 : : * register. While setting the divider bits, higher 16-bit should also be
584 : : * updated to indicate changing divider bits.
585 : : * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
586 : : * to the closest integer instead of the up one.
587 : : * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
588 : : * not be changed by the clock framework.
589 : : * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
590 : : * except when the value read from the register is zero, the divisor is
591 : : * 2^width of the field.
592 : : * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
593 : : * for the divider register. Setting this flag makes the register accesses
594 : : * big endian.
595 : : */
596 : : struct clk_divider {
597 : : struct clk_hw hw;
598 : : void __iomem *reg;
599 : : u8 shift;
600 : : u8 width;
601 : : u8 flags;
602 : : const struct clk_div_table *table;
603 : : spinlock_t *lock;
604 : : };
605 : :
606 : : #define clk_div_mask(width) ((1 << (width)) - 1)
607 : : #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
608 : :
609 : : #define CLK_DIVIDER_ONE_BASED BIT(0)
610 : : #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
611 : : #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
612 : : #define CLK_DIVIDER_HIWORD_MASK BIT(3)
613 : : #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
614 : : #define CLK_DIVIDER_READ_ONLY BIT(5)
615 : : #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
616 : : #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
617 : :
618 : : extern const struct clk_ops clk_divider_ops;
619 : : extern const struct clk_ops clk_divider_ro_ops;
620 : :
621 : : unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
622 : : unsigned int val, const struct clk_div_table *table,
623 : : unsigned long flags, unsigned long width);
624 : : long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
625 : : unsigned long rate, unsigned long *prate,
626 : : const struct clk_div_table *table,
627 : : u8 width, unsigned long flags);
628 : : long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
629 : : unsigned long rate, unsigned long *prate,
630 : : const struct clk_div_table *table, u8 width,
631 : : unsigned long flags, unsigned int val);
632 : : int divider_get_val(unsigned long rate, unsigned long parent_rate,
633 : : const struct clk_div_table *table, u8 width,
634 : : unsigned long flags);
635 : :
636 : : struct clk_hw *__clk_hw_register_divider(struct device *dev,
637 : : struct device_node *np, const char *name,
638 : : const char *parent_name, const struct clk_hw *parent_hw,
639 : : const struct clk_parent_data *parent_data, unsigned long flags,
640 : : void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
641 : : const struct clk_div_table *table, spinlock_t *lock);
642 : : struct clk *clk_register_divider_table(struct device *dev, const char *name,
643 : : const char *parent_name, unsigned long flags,
644 : : void __iomem *reg, u8 shift, u8 width,
645 : : u8 clk_divider_flags, const struct clk_div_table *table,
646 : : spinlock_t *lock);
647 : : /**
648 : : * clk_register_divider - register a divider clock with the clock framework
649 : : * @dev: device registering this clock
650 : : * @name: name of this clock
651 : : * @parent_name: name of clock's parent
652 : : * @flags: framework-specific flags
653 : : * @reg: register address to adjust divider
654 : : * @shift: number of bits to shift the bitfield
655 : : * @width: width of the bitfield
656 : : * @clk_divider_flags: divider-specific flags for this clock
657 : : * @lock: shared register lock for this clock
658 : : */
659 : : #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
660 : : clk_divider_flags, lock) \
661 : : clk_register_divider_table((dev), (name), (parent_name), (flags), \
662 : : (reg), (shift), (width), \
663 : : (clk_divider_flags), NULL, (lock))
664 : : /**
665 : : * clk_hw_register_divider - register a divider clock with the clock framework
666 : : * @dev: device registering this clock
667 : : * @name: name of this clock
668 : : * @parent_name: name of clock's parent
669 : : * @flags: framework-specific flags
670 : : * @reg: register address to adjust divider
671 : : * @shift: number of bits to shift the bitfield
672 : : * @width: width of the bitfield
673 : : * @clk_divider_flags: divider-specific flags for this clock
674 : : * @lock: shared register lock for this clock
675 : : */
676 : : #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
677 : : width, clk_divider_flags, lock) \
678 : : __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
679 : : NULL, (flags), (reg), (shift), (width), \
680 : : (clk_divider_flags), NULL, (lock))
681 : : /**
682 : : * clk_hw_register_divider_parent_hw - register a divider clock with the clock
683 : : * framework
684 : : * @dev: device registering this clock
685 : : * @name: name of this clock
686 : : * @parent_hw: pointer to parent clk
687 : : * @flags: framework-specific flags
688 : : * @reg: register address to adjust divider
689 : : * @shift: number of bits to shift the bitfield
690 : : * @width: width of the bitfield
691 : : * @clk_divider_flags: divider-specific flags for this clock
692 : : * @lock: shared register lock for this clock
693 : : */
694 : : #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
695 : : shift, width, clk_divider_flags, \
696 : : lock) \
697 : : __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
698 : : NULL, (flags), (reg), (shift), (width), \
699 : : (clk_divider_flags), NULL, (lock))
700 : : /**
701 : : * clk_hw_register_divider_parent_data - register a divider clock with the clock
702 : : * framework
703 : : * @dev: device registering this clock
704 : : * @name: name of this clock
705 : : * @parent_data: parent clk data
706 : : * @flags: framework-specific flags
707 : : * @reg: register address to adjust divider
708 : : * @shift: number of bits to shift the bitfield
709 : : * @width: width of the bitfield
710 : : * @clk_divider_flags: divider-specific flags for this clock
711 : : * @lock: shared register lock for this clock
712 : : */
713 : : #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
714 : : reg, shift, width, \
715 : : clk_divider_flags, lock) \
716 : : __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
717 : : (parent_data), (flags), (reg), (shift), \
718 : : (width), (clk_divider_flags), NULL, (lock))
719 : : /**
720 : : * clk_hw_register_divider_table - register a table based divider clock with
721 : : * the clock framework
722 : : * @dev: device registering this clock
723 : : * @name: name of this clock
724 : : * @parent_name: name of clock's parent
725 : : * @flags: framework-specific flags
726 : : * @reg: register address to adjust divider
727 : : * @shift: number of bits to shift the bitfield
728 : : * @width: width of the bitfield
729 : : * @clk_divider_flags: divider-specific flags for this clock
730 : : * @table: array of divider/value pairs ending with a div set to 0
731 : : * @lock: shared register lock for this clock
732 : : */
733 : : #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
734 : : shift, width, clk_divider_flags, table, \
735 : : lock) \
736 : : __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
737 : : NULL, (flags), (reg), (shift), (width), \
738 : : (clk_divider_flags), (table), (lock))
739 : : /**
740 : : * clk_hw_register_divider_table_parent_hw - register a table based divider
741 : : * clock with the clock framework
742 : : * @dev: device registering this clock
743 : : * @name: name of this clock
744 : : * @parent_hw: pointer to parent clk
745 : : * @flags: framework-specific flags
746 : : * @reg: register address to adjust divider
747 : : * @shift: number of bits to shift the bitfield
748 : : * @width: width of the bitfield
749 : : * @clk_divider_flags: divider-specific flags for this clock
750 : : * @table: array of divider/value pairs ending with a div set to 0
751 : : * @lock: shared register lock for this clock
752 : : */
753 : : #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
754 : : reg, shift, width, \
755 : : clk_divider_flags, table, \
756 : : lock) \
757 : : __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
758 : : NULL, (flags), (reg), (shift), (width), \
759 : : (clk_divider_flags), (table), (lock))
760 : : /**
761 : : * clk_hw_register_divider_table_parent_data - register a table based divider
762 : : * clock with the clock framework
763 : : * @dev: device registering this clock
764 : : * @name: name of this clock
765 : : * @parent_data: parent clk data
766 : : * @flags: framework-specific flags
767 : : * @reg: register address to adjust divider
768 : : * @shift: number of bits to shift the bitfield
769 : : * @width: width of the bitfield
770 : : * @clk_divider_flags: divider-specific flags for this clock
771 : : * @table: array of divider/value pairs ending with a div set to 0
772 : : * @lock: shared register lock for this clock
773 : : */
774 : : #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
775 : : flags, reg, shift, width, \
776 : : clk_divider_flags, table, \
777 : : lock) \
778 : : __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
779 : : (parent_data), (flags), (reg), (shift), \
780 : : (width), (clk_divider_flags), (table), \
781 : : (lock))
782 : :
783 : : void clk_unregister_divider(struct clk *clk);
784 : : void clk_hw_unregister_divider(struct clk_hw *hw);
785 : :
786 : : /**
787 : : * struct clk_mux - multiplexer clock
788 : : *
789 : : * @hw: handle between common and hardware-specific interfaces
790 : : * @reg: register controlling multiplexer
791 : : * @table: array of register values corresponding to the parent index
792 : : * @shift: shift to multiplexer bit field
793 : : * @mask: mask of mutliplexer bit field
794 : : * @flags: hardware-specific flags
795 : : * @lock: register lock
796 : : *
797 : : * Clock with multiple selectable parents. Implements .get_parent, .set_parent
798 : : * and .recalc_rate
799 : : *
800 : : * Flags:
801 : : * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
802 : : * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
803 : : * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
804 : : * register, and mask of mux bits are in higher 16-bit of this register.
805 : : * While setting the mux bits, higher 16-bit should also be updated to
806 : : * indicate changing mux bits.
807 : : * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
808 : : * .get_parent clk_op.
809 : : * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
810 : : * frequency.
811 : : * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
812 : : * the mux register. Setting this flag makes the register accesses big
813 : : * endian.
814 : : */
815 : : struct clk_mux {
816 : : struct clk_hw hw;
817 : : void __iomem *reg;
818 : : u32 *table;
819 : : u32 mask;
820 : : u8 shift;
821 : : u8 flags;
822 : : spinlock_t *lock;
823 : : };
824 : :
825 : : #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
826 : :
827 : : #define CLK_MUX_INDEX_ONE BIT(0)
828 : : #define CLK_MUX_INDEX_BIT BIT(1)
829 : : #define CLK_MUX_HIWORD_MASK BIT(2)
830 : : #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
831 : : #define CLK_MUX_ROUND_CLOSEST BIT(4)
832 : : #define CLK_MUX_BIG_ENDIAN BIT(5)
833 : :
834 : : extern const struct clk_ops clk_mux_ops;
835 : : extern const struct clk_ops clk_mux_ro_ops;
836 : :
837 : : struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
838 : : const char *name, u8 num_parents,
839 : : const char * const *parent_names,
840 : : const struct clk_hw **parent_hws,
841 : : const struct clk_parent_data *parent_data,
842 : : unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
843 : : u8 clk_mux_flags, u32 *table, spinlock_t *lock);
844 : : struct clk *clk_register_mux_table(struct device *dev, const char *name,
845 : : const char * const *parent_names, u8 num_parents,
846 : : unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
847 : : u8 clk_mux_flags, u32 *table, spinlock_t *lock);
848 : :
849 : : #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
850 : : shift, width, clk_mux_flags, lock) \
851 : : clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
852 : : (flags), (reg), (shift), BIT((width)) - 1, \
853 : : (clk_mux_flags), NULL, (lock))
854 : : #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
855 : : flags, reg, shift, mask, clk_mux_flags, \
856 : : table, lock) \
857 : : __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
858 : : (parent_names), NULL, NULL, (flags), (reg), \
859 : : (shift), (mask), (clk_mux_flags), (table), \
860 : : (lock))
861 : : #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
862 : : shift, width, clk_mux_flags, lock) \
863 : : __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
864 : : (parent_names), NULL, NULL, (flags), (reg), \
865 : : (shift), BIT((width)) - 1, (clk_mux_flags), \
866 : : NULL, (lock))
867 : : #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
868 : : reg, shift, width, clk_mux_flags, lock) \
869 : : __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
870 : : (parent_hws), NULL, (flags), (reg), (shift), \
871 : : BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
872 : : #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
873 : : flags, reg, shift, width, \
874 : : clk_mux_flags, lock) \
875 : : __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
876 : : (parent_data), (flags), (reg), (shift), \
877 : : BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
878 : :
879 : : int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
880 : : unsigned int val);
881 : : unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
882 : :
883 : : void clk_unregister_mux(struct clk *clk);
884 : : void clk_hw_unregister_mux(struct clk_hw *hw);
885 : :
886 : : void of_fixed_factor_clk_setup(struct device_node *node);
887 : :
888 : : /**
889 : : * struct clk_fixed_factor - fixed multiplier and divider clock
890 : : *
891 : : * @hw: handle between common and hardware-specific interfaces
892 : : * @mult: multiplier
893 : : * @div: divider
894 : : *
895 : : * Clock with a fixed multiplier and divider. The output frequency is the
896 : : * parent clock rate divided by div and multiplied by mult.
897 : : * Implements .recalc_rate, .set_rate and .round_rate
898 : : */
899 : :
900 : : struct clk_fixed_factor {
901 : : struct clk_hw hw;
902 : : unsigned int mult;
903 : : unsigned int div;
904 : : };
905 : :
906 : : #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
907 : :
908 : : extern const struct clk_ops clk_fixed_factor_ops;
909 : : struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
910 : : const char *parent_name, unsigned long flags,
911 : : unsigned int mult, unsigned int div);
912 : : void clk_unregister_fixed_factor(struct clk *clk);
913 : : struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
914 : : const char *name, const char *parent_name, unsigned long flags,
915 : : unsigned int mult, unsigned int div);
916 : : void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
917 : :
918 : : /**
919 : : * struct clk_fractional_divider - adjustable fractional divider clock
920 : : *
921 : : * @hw: handle between common and hardware-specific interfaces
922 : : * @reg: register containing the divider
923 : : * @mshift: shift to the numerator bit field
924 : : * @mwidth: width of the numerator bit field
925 : : * @nshift: shift to the denominator bit field
926 : : * @nwidth: width of the denominator bit field
927 : : * @lock: register lock
928 : : *
929 : : * Clock with adjustable fractional divider affecting its output frequency.
930 : : *
931 : : * Flags:
932 : : * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
933 : : * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
934 : : * is set then the numerator and denominator are both the value read
935 : : * plus one.
936 : : * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
937 : : * used for the divider register. Setting this flag makes the register
938 : : * accesses big endian.
939 : : */
940 : : struct clk_fractional_divider {
941 : : struct clk_hw hw;
942 : : void __iomem *reg;
943 : : u8 mshift;
944 : : u8 mwidth;
945 : : u32 mmask;
946 : : u8 nshift;
947 : : u8 nwidth;
948 : : u32 nmask;
949 : : u8 flags;
950 : : void (*approximation)(struct clk_hw *hw,
951 : : unsigned long rate, unsigned long *parent_rate,
952 : : unsigned long *m, unsigned long *n);
953 : : spinlock_t *lock;
954 : : };
955 : :
956 : : #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
957 : :
958 : : #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
959 : : #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
960 : :
961 : : extern const struct clk_ops clk_fractional_divider_ops;
962 : : struct clk *clk_register_fractional_divider(struct device *dev,
963 : : const char *name, const char *parent_name, unsigned long flags,
964 : : void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
965 : : u8 clk_divider_flags, spinlock_t *lock);
966 : : struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
967 : : const char *name, const char *parent_name, unsigned long flags,
968 : : void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
969 : : u8 clk_divider_flags, spinlock_t *lock);
970 : : void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
971 : :
972 : : /**
973 : : * struct clk_multiplier - adjustable multiplier clock
974 : : *
975 : : * @hw: handle between common and hardware-specific interfaces
976 : : * @reg: register containing the multiplier
977 : : * @shift: shift to the multiplier bit field
978 : : * @width: width of the multiplier bit field
979 : : * @lock: register lock
980 : : *
981 : : * Clock with an adjustable multiplier affecting its output frequency.
982 : : * Implements .recalc_rate, .set_rate and .round_rate
983 : : *
984 : : * Flags:
985 : : * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
986 : : * from the register, with 0 being a valid value effectively
987 : : * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
988 : : * set, then a null multiplier will be considered as a bypass,
989 : : * leaving the parent rate unmodified.
990 : : * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
991 : : * rounded to the closest integer instead of the down one.
992 : : * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
993 : : * used for the multiplier register. Setting this flag makes the register
994 : : * accesses big endian.
995 : : */
996 : : struct clk_multiplier {
997 : : struct clk_hw hw;
998 : : void __iomem *reg;
999 : : u8 shift;
1000 : : u8 width;
1001 : : u8 flags;
1002 : : spinlock_t *lock;
1003 : : };
1004 : :
1005 : : #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1006 : :
1007 : : #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1008 : : #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1009 : : #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1010 : :
1011 : : extern const struct clk_ops clk_multiplier_ops;
1012 : :
1013 : : /***
1014 : : * struct clk_composite - aggregate clock of mux, divider and gate clocks
1015 : : *
1016 : : * @hw: handle between common and hardware-specific interfaces
1017 : : * @mux_hw: handle between composite and hardware-specific mux clock
1018 : : * @rate_hw: handle between composite and hardware-specific rate clock
1019 : : * @gate_hw: handle between composite and hardware-specific gate clock
1020 : : * @mux_ops: clock ops for mux
1021 : : * @rate_ops: clock ops for rate
1022 : : * @gate_ops: clock ops for gate
1023 : : */
1024 : : struct clk_composite {
1025 : : struct clk_hw hw;
1026 : : struct clk_ops ops;
1027 : :
1028 : : struct clk_hw *mux_hw;
1029 : : struct clk_hw *rate_hw;
1030 : : struct clk_hw *gate_hw;
1031 : :
1032 : : const struct clk_ops *mux_ops;
1033 : : const struct clk_ops *rate_ops;
1034 : : const struct clk_ops *gate_ops;
1035 : : };
1036 : :
1037 : : #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1038 : :
1039 : : struct clk *clk_register_composite(struct device *dev, const char *name,
1040 : : const char * const *parent_names, int num_parents,
1041 : : struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1042 : : struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1043 : : struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1044 : : unsigned long flags);
1045 : : struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1046 : : const struct clk_parent_data *parent_data, int num_parents,
1047 : : struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1048 : : struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1049 : : struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1050 : : unsigned long flags);
1051 : : void clk_unregister_composite(struct clk *clk);
1052 : : struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1053 : : const char * const *parent_names, int num_parents,
1054 : : struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1055 : : struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1056 : : struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1057 : : unsigned long flags);
1058 : : struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1059 : : const char *name,
1060 : : const struct clk_parent_data *parent_data, int num_parents,
1061 : : struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1062 : : struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1063 : : struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1064 : : unsigned long flags);
1065 : : void clk_hw_unregister_composite(struct clk_hw *hw);
1066 : :
1067 : : struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1068 : : struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1069 : :
1070 : : int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1071 : : int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1072 : : int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1073 : :
1074 : : void clk_unregister(struct clk *clk);
1075 : : void devm_clk_unregister(struct device *dev, struct clk *clk);
1076 : :
1077 : : void clk_hw_unregister(struct clk_hw *hw);
1078 : : void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1079 : :
1080 : : /* helper functions */
1081 : : const char *__clk_get_name(const struct clk *clk);
1082 : : const char *clk_hw_get_name(const struct clk_hw *hw);
1083 : : #ifdef CONFIG_COMMON_CLK
1084 : : struct clk_hw *__clk_get_hw(struct clk *clk);
1085 : : #else
1086 : : static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1087 : : {
1088 : : return (struct clk_hw *)clk;
1089 : : }
1090 : : #endif
1091 : : unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1092 : : struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1093 : : struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1094 : : unsigned int index);
1095 : : int clk_hw_get_parent_index(struct clk_hw *hw);
1096 : : int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1097 : : unsigned int __clk_get_enable_count(struct clk *clk);
1098 : : unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1099 : : unsigned long __clk_get_flags(struct clk *clk);
1100 : : unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1101 : : #define clk_hw_can_set_rate_parent(hw) \
1102 : : (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1103 : :
1104 : : bool clk_hw_is_prepared(const struct clk_hw *hw);
1105 : : bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1106 : : bool clk_hw_is_enabled(const struct clk_hw *hw);
1107 : : bool __clk_is_enabled(struct clk *clk);
1108 : : struct clk *__clk_lookup(const char *name);
1109 : : int __clk_mux_determine_rate(struct clk_hw *hw,
1110 : : struct clk_rate_request *req);
1111 : : int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1112 : : int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1113 : : struct clk_rate_request *req);
1114 : : int clk_mux_determine_rate_flags(struct clk_hw *hw,
1115 : : struct clk_rate_request *req,
1116 : : unsigned long flags);
1117 : : void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1118 : : void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1119 : : unsigned long max_rate);
1120 : :
1121 : 0 : static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1122 : : {
1123 : 0 : dst->clk = src->clk;
1124 : 0 : dst->core = src->core;
1125 : : }
1126 : :
1127 : 0 : static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1128 : : unsigned long *prate,
1129 : : const struct clk_div_table *table,
1130 : : u8 width, unsigned long flags)
1131 : : {
1132 : 0 : return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1133 : : rate, prate, table, width, flags);
1134 : : }
1135 : :
1136 : 0 : static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1137 : : unsigned long *prate,
1138 : : const struct clk_div_table *table,
1139 : : u8 width, unsigned long flags,
1140 : : unsigned int val)
1141 : : {
1142 : 0 : return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1143 : : rate, prate, table, width, flags,
1144 : : val);
1145 : : }
1146 : :
1147 : : /*
1148 : : * FIXME clock api without lock protection
1149 : : */
1150 : : unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1151 : :
1152 : : struct clk_onecell_data {
1153 : : struct clk **clks;
1154 : : unsigned int clk_num;
1155 : : };
1156 : :
1157 : : struct clk_hw_onecell_data {
1158 : : unsigned int num;
1159 : : struct clk_hw *hws[];
1160 : : };
1161 : :
1162 : : #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1163 : :
1164 : : /*
1165 : : * Use this macro when you have a driver that requires two initialization
1166 : : * routines, one at of_clk_init(), and one at platform device probe
1167 : : */
1168 : : #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1169 : : static void __init name##_of_clk_init_driver(struct device_node *np) \
1170 : : { \
1171 : : of_node_clear_flag(np, OF_POPULATED); \
1172 : : fn(np); \
1173 : : } \
1174 : : OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1175 : :
1176 : : #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1177 : : (&(struct clk_init_data) { \
1178 : : .flags = _flags, \
1179 : : .name = _name, \
1180 : : .parent_names = (const char *[]) { _parent }, \
1181 : : .num_parents = 1, \
1182 : : .ops = _ops, \
1183 : : })
1184 : :
1185 : : #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1186 : : (&(struct clk_init_data) { \
1187 : : .flags = _flags, \
1188 : : .name = _name, \
1189 : : .parent_hws = (const struct clk_hw*[]) { _parent }, \
1190 : : .num_parents = 1, \
1191 : : .ops = _ops, \
1192 : : })
1193 : :
1194 : : /*
1195 : : * This macro is intended for drivers to be able to share the otherwise
1196 : : * individual struct clk_hw[] compound literals created by the compiler
1197 : : * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1198 : : */
1199 : : #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1200 : : (&(struct clk_init_data) { \
1201 : : .flags = _flags, \
1202 : : .name = _name, \
1203 : : .parent_hws = _parent, \
1204 : : .num_parents = 1, \
1205 : : .ops = _ops, \
1206 : : })
1207 : :
1208 : : #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1209 : : (&(struct clk_init_data) { \
1210 : : .flags = _flags, \
1211 : : .name = _name, \
1212 : : .parent_data = (const struct clk_parent_data[]) { \
1213 : : { .fw_name = _parent }, \
1214 : : }, \
1215 : : .num_parents = 1, \
1216 : : .ops = _ops, \
1217 : : })
1218 : :
1219 : : #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1220 : : (&(struct clk_init_data) { \
1221 : : .flags = _flags, \
1222 : : .name = _name, \
1223 : : .parent_names = _parents, \
1224 : : .num_parents = ARRAY_SIZE(_parents), \
1225 : : .ops = _ops, \
1226 : : })
1227 : :
1228 : : #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1229 : : (&(struct clk_init_data) { \
1230 : : .flags = _flags, \
1231 : : .name = _name, \
1232 : : .parent_hws = _parents, \
1233 : : .num_parents = ARRAY_SIZE(_parents), \
1234 : : .ops = _ops, \
1235 : : })
1236 : :
1237 : : #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1238 : : (&(struct clk_init_data) { \
1239 : : .flags = _flags, \
1240 : : .name = _name, \
1241 : : .parent_data = _parents, \
1242 : : .num_parents = ARRAY_SIZE(_parents), \
1243 : : .ops = _ops, \
1244 : : })
1245 : :
1246 : : #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1247 : : (&(struct clk_init_data) { \
1248 : : .flags = _flags, \
1249 : : .name = _name, \
1250 : : .parent_names = NULL, \
1251 : : .num_parents = 0, \
1252 : : .ops = _ops, \
1253 : : })
1254 : :
1255 : : #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1256 : : _div, _mult, _flags) \
1257 : : struct clk_fixed_factor _struct = { \
1258 : : .div = _div, \
1259 : : .mult = _mult, \
1260 : : .hw.init = CLK_HW_INIT(_name, \
1261 : : _parent, \
1262 : : &clk_fixed_factor_ops, \
1263 : : _flags), \
1264 : : }
1265 : :
1266 : : #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1267 : : _div, _mult, _flags) \
1268 : : struct clk_fixed_factor _struct = { \
1269 : : .div = _div, \
1270 : : .mult = _mult, \
1271 : : .hw.init = CLK_HW_INIT_HW(_name, \
1272 : : _parent, \
1273 : : &clk_fixed_factor_ops, \
1274 : : _flags), \
1275 : : }
1276 : :
1277 : : /*
1278 : : * This macro allows the driver to reuse the _parent array for multiple
1279 : : * fixed factor clk declarations.
1280 : : */
1281 : : #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1282 : : _div, _mult, _flags) \
1283 : : struct clk_fixed_factor _struct = { \
1284 : : .div = _div, \
1285 : : .mult = _mult, \
1286 : : .hw.init = CLK_HW_INIT_HWS(_name, \
1287 : : _parent, \
1288 : : &clk_fixed_factor_ops, \
1289 : : _flags), \
1290 : : }
1291 : :
1292 : : #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1293 : : _div, _mult, _flags) \
1294 : : struct clk_fixed_factor _struct = { \
1295 : : .div = _div, \
1296 : : .mult = _mult, \
1297 : : .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1298 : : _parent, \
1299 : : &clk_fixed_factor_ops, \
1300 : : _flags), \
1301 : : }
1302 : :
1303 : : #ifdef CONFIG_OF
1304 : : int of_clk_add_provider(struct device_node *np,
1305 : : struct clk *(*clk_src_get)(struct of_phandle_args *args,
1306 : : void *data),
1307 : : void *data);
1308 : : int of_clk_add_hw_provider(struct device_node *np,
1309 : : struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1310 : : void *data),
1311 : : void *data);
1312 : : int devm_of_clk_add_hw_provider(struct device *dev,
1313 : : struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1314 : : void *data),
1315 : : void *data);
1316 : : void of_clk_del_provider(struct device_node *np);
1317 : : void devm_of_clk_del_provider(struct device *dev);
1318 : : struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1319 : : void *data);
1320 : : struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1321 : : void *data);
1322 : : struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1323 : : struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1324 : : void *data);
1325 : : int of_clk_parent_fill(struct device_node *np, const char **parents,
1326 : : unsigned int size);
1327 : : int of_clk_detect_critical(struct device_node *np, int index,
1328 : : unsigned long *flags);
1329 : :
1330 : : #else /* !CONFIG_OF */
1331 : :
1332 : : static inline int of_clk_add_provider(struct device_node *np,
1333 : : struct clk *(*clk_src_get)(struct of_phandle_args *args,
1334 : : void *data),
1335 : : void *data)
1336 : : {
1337 : : return 0;
1338 : : }
1339 : : static inline int of_clk_add_hw_provider(struct device_node *np,
1340 : : struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1341 : : void *data),
1342 : : void *data)
1343 : : {
1344 : : return 0;
1345 : : }
1346 : : static inline int devm_of_clk_add_hw_provider(struct device *dev,
1347 : : struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1348 : : void *data),
1349 : : void *data)
1350 : : {
1351 : : return 0;
1352 : : }
1353 : : static inline void of_clk_del_provider(struct device_node *np) {}
1354 : : static inline void devm_of_clk_del_provider(struct device *dev) {}
1355 : : static inline struct clk *of_clk_src_simple_get(
1356 : : struct of_phandle_args *clkspec, void *data)
1357 : : {
1358 : : return ERR_PTR(-ENOENT);
1359 : : }
1360 : : static inline struct clk_hw *
1361 : : of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1362 : : {
1363 : : return ERR_PTR(-ENOENT);
1364 : : }
1365 : : static inline struct clk *of_clk_src_onecell_get(
1366 : : struct of_phandle_args *clkspec, void *data)
1367 : : {
1368 : : return ERR_PTR(-ENOENT);
1369 : : }
1370 : : static inline struct clk_hw *
1371 : : of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1372 : : {
1373 : : return ERR_PTR(-ENOENT);
1374 : : }
1375 : : static inline int of_clk_parent_fill(struct device_node *np,
1376 : : const char **parents, unsigned int size)
1377 : : {
1378 : : return 0;
1379 : : }
1380 : : static inline int of_clk_detect_critical(struct device_node *np, int index,
1381 : : unsigned long *flags)
1382 : : {
1383 : : return 0;
1384 : : }
1385 : : #endif /* CONFIG_OF */
1386 : :
1387 : : void clk_gate_restore_context(struct clk_hw *hw);
1388 : :
1389 : : #endif /* CLK_PROVIDER_H */
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