Branch data Line data Source code
1 : : /*
2 : : *
3 : : * Copyright 2008 (c) Intel Corporation
4 : : * Jesse Barnes <jbarnes@virtuousgeek.org>
5 : : *
6 : : * Permission is hereby granted, free of charge, to any person obtaining a
7 : : * copy of this software and associated documentation files (the
8 : : * "Software"), to deal in the Software without restriction, including
9 : : * without limitation the rights to use, copy, modify, merge, publish,
10 : : * distribute, sub license, and/or sell copies of the Software, and to
11 : : * permit persons to whom the Software is furnished to do so, subject to
12 : : * the following conditions:
13 : : *
14 : : * The above copyright notice and this permission notice (including the
15 : : * next paragraph) shall be included in all copies or substantial portions
16 : : * of the Software.
17 : : *
18 : : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 : : * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 : : * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 : : * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 : : * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 : : * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 : : * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 : : */
26 : :
27 : : #include <drm/i915_drm.h>
28 : :
29 : : #include "display/intel_fbc.h"
30 : : #include "display/intel_gmbus.h"
31 : : #include "display/intel_vga.h"
32 : :
33 : : #include "i915_drv.h"
34 : : #include "i915_reg.h"
35 : : #include "i915_suspend.h"
36 : :
37 : 0 : static void i915_save_display(struct drm_i915_private *dev_priv)
38 : : {
39 : : /* Display arbitration control */
40 [ # # ]: 0 : if (INTEL_GEN(dev_priv) <= 4)
41 : 0 : dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
42 : :
43 : : /* save FBC interval */
44 [ # # # # : 0 : if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
# # # # ]
45 : 0 : dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
46 : 0 : }
47 : :
48 : 0 : static void i915_restore_display(struct drm_i915_private *dev_priv)
49 : : {
50 : : /* Display arbitration */
51 [ # # ]: 0 : if (INTEL_GEN(dev_priv) <= 4)
52 : 0 : I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
53 : :
54 : : /* only restore FBC info on the platform that supports FBC*/
55 : 0 : intel_fbc_global_disable(dev_priv);
56 : :
57 : : /* restore FBC interval */
58 [ # # # # : 0 : if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
# # # # ]
59 : 0 : I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
60 : :
61 : 0 : intel_vga_redisable(dev_priv);
62 : 0 : }
63 : :
64 : 0 : int i915_save_state(struct drm_i915_private *dev_priv)
65 : : {
66 : 0 : struct pci_dev *pdev = dev_priv->drm.pdev;
67 : 0 : int i;
68 : :
69 : 0 : i915_save_display(dev_priv);
70 : :
71 [ # # ]: 0 : if (IS_GEN(dev_priv, 4))
72 : 0 : pci_read_config_word(pdev, GCDGMBUS,
73 : : &dev_priv->regfile.saveGCDGMBUS);
74 : :
75 : : /* Cache mode state */
76 [ # # ]: 0 : if (INTEL_GEN(dev_priv) < 7)
77 : 0 : dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
78 : :
79 : : /* Memory Arbitration state */
80 : 0 : dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
81 : :
82 : : /* Scratch space */
83 [ # # # # ]: 0 : if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
84 [ # # ]: 0 : for (i = 0; i < 7; i++) {
85 : 0 : dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
86 : 0 : dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
87 : : }
88 [ # # ]: 0 : for (i = 0; i < 3; i++)
89 : 0 : dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
90 [ # # ]: 0 : } else if (IS_GEN(dev_priv, 2)) {
91 [ # # ]: 0 : for (i = 0; i < 7; i++)
92 : 0 : dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
93 [ # # ]: 0 : } else if (HAS_GMCH(dev_priv)) {
94 [ # # ]: 0 : for (i = 0; i < 16; i++) {
95 : 0 : dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
96 : 0 : dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
97 : : }
98 [ # # ]: 0 : for (i = 0; i < 3; i++)
99 : 0 : dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
100 : : }
101 : :
102 : 0 : return 0;
103 : : }
104 : :
105 : 0 : int i915_restore_state(struct drm_i915_private *dev_priv)
106 : : {
107 : 0 : struct pci_dev *pdev = dev_priv->drm.pdev;
108 : 0 : int i;
109 : :
110 [ # # ]: 0 : if (IS_GEN(dev_priv, 4))
111 : 0 : pci_write_config_word(pdev, GCDGMBUS,
112 : 0 : dev_priv->regfile.saveGCDGMBUS);
113 : 0 : i915_restore_display(dev_priv);
114 : :
115 : : /* Cache mode state */
116 [ # # ]: 0 : if (INTEL_GEN(dev_priv) < 7)
117 : 0 : I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
118 : : 0xffff0000);
119 : :
120 : : /* Memory arbitration state */
121 : 0 : I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
122 : :
123 : : /* Scratch space */
124 [ # # # # ]: 0 : if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
125 [ # # ]: 0 : for (i = 0; i < 7; i++) {
126 : 0 : I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
127 : 0 : I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
128 : : }
129 [ # # ]: 0 : for (i = 0; i < 3; i++)
130 : 0 : I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
131 [ # # ]: 0 : } else if (IS_GEN(dev_priv, 2)) {
132 [ # # ]: 0 : for (i = 0; i < 7; i++)
133 : 0 : I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
134 [ # # ]: 0 : } else if (HAS_GMCH(dev_priv)) {
135 [ # # ]: 0 : for (i = 0; i < 16; i++) {
136 : 0 : I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
137 : 0 : I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
138 : : }
139 [ # # ]: 0 : for (i = 0; i < 3; i++)
140 : 0 : I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
141 : : }
142 : :
143 : 0 : intel_gmbus_reset(dev_priv);
144 : :
145 : 0 : return 0;
146 : : }
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