LCOV - code coverage report

Current view: top level - drivers/gpu/drm/i915 - intel_pm.c (source / functions) Hit Total Coverage Test: combined.info Lines: 0 3015 0.0 % Date: 2022-03-28 16:04:14 Functions: 0 158 0.0 % Branches: 0 2027 0.0 %

Function Name	Hit count
_ilk_disable_lp_wm	0
_intel_set_memory_cxsr	0
bdw_init_clock_gating	0
bxt_init_clock_gating	0
cfl_init_clock_gating	0
chv_init_clock_gating	0
chv_set_memory_dvfs	0
chv_set_memory_pm5	0
cnl_init_clock_gating	0
cnp_init_clock_gating	0
cpt_init_clock_gating	0
g4x_compute_intermediate_wm	0
g4x_compute_pipe_wm	0
g4x_compute_wm	0
g4x_disable_trickle_feed	0
g4x_fbc_fifo_size	0
g4x_init_clock_gating	0
g4x_initial_watermarks	0
g4x_merge_wm	0
g4x_optimize_watermarks	0
g4x_plane_fifo_size	0
g4x_program_watermarks	0
g4x_raw_crtc_wm_is_valid	0
g4x_raw_plane_wm_compute	0
g4x_read_wm_values	0
g4x_wm_get_hw_state	0
g4x_wm_sanitize	0
g4x_write_wm_values	0
gen3_init_clock_gating	0
gen6_check_mch_setup	0
gen6_init_clock_gating	0
gen7_setup_fixed_func_scheduler	0
gen8_set_l3sqc_credits	0
gen9_init_clock_gating	0
glk_init_clock_gating	0
hsw_compute_linetime_wm	0
hsw_init_clock_gating	0
i830_get_fifo_size	0
i830_init_clock_gating	0
i845_get_fifo_size	0
i845_update_wm	0
i85x_init_clock_gating	0
i965_update_wm	0
i965g_init_clock_gating	0
i965gm_init_clock_gating	0
i9xx_get_fifo_size	0
i9xx_update_wm	0
icl_build_plane_wm	0
icl_get_total_relative_data_rate	0
icl_init_clock_gating	0
ilk_compute_cur_wm	0
ilk_compute_fbc_wm	0
ilk_compute_intermediate_wm	0
ilk_compute_pipe_wm	0
ilk_compute_pri_wm	0
ilk_compute_spr_wm	0
ilk_compute_wm_maximums	0
ilk_compute_wm_results	0
ilk_disable_lp_wm	0
ilk_find_best_result	0
ilk_get_mem_freq	0
ilk_increase_wm_latency	0
ilk_init_clock_gating	0
ilk_init_lp_watermarks	0
ilk_initial_watermarks	0
ilk_merge_wm_level	0
ilk_optimize_watermarks	0
ilk_pipe_wm_get_hw_state	0
ilk_plane_wm_max	0
ilk_program_watermarks	0
ilk_setup_wm_latency	0
ilk_validate_pipe_wm	0
ilk_validate_wm_level	0
ilk_wm_fbc	0
ilk_wm_get_hw_state	0
ilk_wm_max_level	0
ilk_write_wm_values	0
intel_add_all_pipes	0
intel_calculate_wm	0
intel_can_enable_sagv	0
intel_disable_sagv	0
intel_enable_ipc	0
intel_enable_sagv	0
intel_get_cxsr_latency	0
intel_get_linetime_us	0
intel_init_clock_gating	0
intel_init_clock_gating_hooks	0
intel_init_ipc	0
intel_init_pm	0
intel_pm_setup	0
intel_print_wm_latency	0
intel_read_wm_latency	0
intel_set_memory_cxsr	0
intel_suspend_hw	0
intel_update_watermarks	0
intel_wm_method2	0
ivb_init_clock_gating	0
kbl_init_clock_gating	0
lpt_init_clock_gating	0
lpt_suspend_hw	0
nop_init_clock_gating	0
pnv_get_mem_freq	0
pnv_update_wm	0
single_enabled_crtc	0
skl_adjusted_plane_pixel_rate	0
skl_allocate_pipe_ddb	0
skl_atomic_update_crtc_wm	0
skl_build_pipe_wm	0
skl_build_plane_wm	0
skl_build_plane_wm_single	0
skl_build_plane_wm_uv	0
skl_compute_ddb	0
skl_compute_linetime_wm	0
skl_compute_plane_wm_params	0
skl_compute_wm	0
skl_compute_wm_levels	0
skl_compute_wm_params	0
skl_cursor_allocation	0
skl_ddb_add_affected_pipes	0
skl_ddb_add_affected_planes	0
skl_ddb_allocation_overlaps	0
skl_ddb_get_hw_plane_state	0
skl_ddb_get_hw_state	0
skl_get_total_relative_data_rate	0
skl_init_clock_gating	0
skl_initial_wm	0
skl_pipe_ddb_get_hw_state	0
skl_pipe_wm_get_hw_state	0
skl_plane_downscale_amount	0
skl_plane_relative_data_rate	0
skl_plane_wm_equals	0
skl_setup_sagv_block_time	0
skl_setup_wm_latency	0
skl_wm_add_affected_planes	0
skl_wm_get_hw_state	0
skl_wm_level_equals	0
skl_wm_method1	0
skl_write_cursor_wm	0
skl_write_plane_wm	0
snb_wm_latency_quirk	0
snb_wm_lp3_irq_quirk	0
tgl_init_clock_gating	0
vlv_atomic_update_fifo	0
vlv_compute_fifo	0
vlv_compute_intermediate_wm	0
vlv_compute_pipe_wm	0
vlv_compute_wm_level	0
vlv_get_fifo_size	0
vlv_init_clock_gating	0
vlv_initial_watermarks	0
vlv_merge_wm	0
vlv_optimize_watermarks	0
vlv_program_watermarks	0
vlv_raw_plane_wm_compute	0
vlv_read_wm_values	0
vlv_wm_get_hw_state	0
vlv_wm_sanitize	0
vlv_write_wm_values	0

Generated by: LCOV version 1.14