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1 : : /* SPDX-License-Identifier: GPL-2.0-or-later */
2 : : /*
3 : : * ahci.h - Common AHCI SATA definitions and declarations
4 : : *
5 : : * Maintained by: Tejun Heo <tj@kernel.org>
6 : : * Please ALWAYS copy linux-ide@vger.kernel.org
7 : : * on emails.
8 : : *
9 : : * Copyright 2004-2005 Red Hat, Inc.
10 : : *
11 : : * libata documentation is available via 'make {ps|pdf}docs',
12 : : * as Documentation/driver-api/libata.rst
13 : : *
14 : : * AHCI hardware documentation:
15 : : * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 : : * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 : : */
18 : :
19 : : #ifndef _AHCI_H
20 : : #define _AHCI_H
21 : :
22 : : #include <linux/pci.h>
23 : : #include <linux/clk.h>
24 : : #include <linux/libata.h>
25 : : #include <linux/phy/phy.h>
26 : : #include <linux/regulator/consumer.h>
27 : :
28 : : /* Enclosure Management Control */
29 : : #define EM_CTRL_MSG_TYPE 0x000f0000
30 : :
31 : : /* Enclosure Management LED Message Type */
32 : : #define EM_MSG_LED_HBA_PORT 0x0000000f
33 : : #define EM_MSG_LED_PMP_SLOT 0x0000ff00
34 : : #define EM_MSG_LED_VALUE 0xffff0000
35 : : #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
36 : : #define EM_MSG_LED_VALUE_OFF 0xfff80000
37 : : #define EM_MSG_LED_VALUE_ON 0x00010000
38 : :
39 : : enum {
40 : : AHCI_MAX_PORTS = 32,
41 : : AHCI_MAX_CLKS = 5,
42 : : AHCI_MAX_SG = 168, /* hardware max is 64K */
43 : : AHCI_DMA_BOUNDARY = 0xffffffff,
44 : : AHCI_MAX_CMDS = 32,
45 : : AHCI_CMD_SZ = 32,
46 : : AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
47 : : AHCI_RX_FIS_SZ = 256,
48 : : AHCI_CMD_TBL_CDB = 0x40,
49 : : AHCI_CMD_TBL_HDR_SZ = 0x80,
50 : : AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
51 : : AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
52 : : AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
53 : : AHCI_RX_FIS_SZ,
54 : : AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
55 : : AHCI_CMD_TBL_AR_SZ +
56 : : (AHCI_RX_FIS_SZ * 16),
57 : : AHCI_IRQ_ON_SG = (1 << 31),
58 : : AHCI_CMD_ATAPI = (1 << 5),
59 : : AHCI_CMD_WRITE = (1 << 6),
60 : : AHCI_CMD_PREFETCH = (1 << 7),
61 : : AHCI_CMD_RESET = (1 << 8),
62 : : AHCI_CMD_CLR_BUSY = (1 << 10),
63 : :
64 : : RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
65 : : RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
66 : : RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
67 : : RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
68 : :
69 : : /* global controller registers */
70 : : HOST_CAP = 0x00, /* host capabilities */
71 : : HOST_CTL = 0x04, /* global host control */
72 : : HOST_IRQ_STAT = 0x08, /* interrupt status */
73 : : HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
74 : : HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
75 : : HOST_EM_LOC = 0x1c, /* Enclosure Management location */
76 : : HOST_EM_CTL = 0x20, /* Enclosure Management Control */
77 : : HOST_CAP2 = 0x24, /* host capabilities, extended */
78 : :
79 : : /* HOST_CTL bits */
80 : : HOST_RESET = (1 << 0), /* reset controller; self-clear */
81 : : HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
82 : : HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */
83 : : HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
84 : :
85 : : /* HOST_CAP bits */
86 : : HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
87 : : HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
88 : : HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
89 : : HOST_CAP_PART = (1 << 13), /* Partial state capable */
90 : : HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
91 : : HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
92 : : HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
93 : : HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
94 : : HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
95 : : HOST_CAP_CLO = (1 << 24), /* Command List Override support */
96 : : HOST_CAP_LED = (1 << 25), /* Supports activity LED */
97 : : HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
98 : : HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
99 : : HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
100 : : HOST_CAP_SNTF = (1 << 29), /* SNotification register */
101 : : HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
102 : : HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
103 : :
104 : : /* HOST_CAP2 bits */
105 : : HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
106 : : HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
107 : : HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
108 : : HOST_CAP2_SDS = (1 << 3), /* Support device sleep */
109 : : HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */
110 : : HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */
111 : :
112 : : /* registers for each SATA port */
113 : : PORT_LST_ADDR = 0x00, /* command list DMA addr */
114 : : PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
115 : : PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
116 : : PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
117 : : PORT_IRQ_STAT = 0x10, /* interrupt status */
118 : : PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
119 : : PORT_CMD = 0x18, /* port command */
120 : : PORT_TFDATA = 0x20, /* taskfile data */
121 : : PORT_SIG = 0x24, /* device TF signature */
122 : : PORT_CMD_ISSUE = 0x38, /* command issue */
123 : : PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
124 : : PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
125 : : PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
126 : : PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
127 : : PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
128 : : PORT_FBS = 0x40, /* FIS-based Switching */
129 : : PORT_DEVSLP = 0x44, /* device sleep */
130 : :
131 : : /* PORT_IRQ_{STAT,MASK} bits */
132 : : PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
133 : : PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
134 : : PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
135 : : PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
136 : : PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
137 : : PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
138 : : PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
139 : : PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
140 : :
141 : : PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
142 : : PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
143 : : PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
144 : : PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
145 : : PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
146 : : PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
147 : : PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
148 : : PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
149 : : PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
150 : :
151 : : PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
152 : : PORT_IRQ_IF_ERR |
153 : : PORT_IRQ_CONNECT |
154 : : PORT_IRQ_PHYRDY |
155 : : PORT_IRQ_UNK_FIS |
156 : : PORT_IRQ_BAD_PMP,
157 : : PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
158 : : PORT_IRQ_TF_ERR |
159 : : PORT_IRQ_HBUS_DATA_ERR,
160 : : DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
161 : : PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
162 : : PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
163 : :
164 : : /* PORT_CMD bits */
165 : : PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
166 : : PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
167 : : PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
168 : : PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
169 : : PORT_CMD_ESP = (1 << 21), /* External Sata Port */
170 : : PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */
171 : : PORT_CMD_PMP = (1 << 17), /* PMP attached */
172 : : PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
173 : : PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
174 : : PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
175 : : PORT_CMD_CLO = (1 << 3), /* Command list override */
176 : : PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
177 : : PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
178 : : PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
179 : :
180 : : PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
181 : : PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
182 : : PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
183 : : PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
184 : :
185 : : /* PORT_FBS bits */
186 : : PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
187 : : PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
188 : : PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
189 : : PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
190 : : PORT_FBS_SDE = (1 << 2), /* FBS single device error */
191 : : PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
192 : : PORT_FBS_EN = (1 << 0), /* Enable FBS */
193 : :
194 : : /* PORT_DEVSLP bits */
195 : : PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */
196 : : PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */
197 : : PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */
198 : : PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */
199 : : PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */
200 : : PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */
201 : : PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */
202 : :
203 : : /* hpriv->flags bits */
204 : :
205 : : #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
206 : :
207 : : AHCI_HFLAG_NO_NCQ = (1 << 0),
208 : : AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
209 : : AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
210 : : AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
211 : : AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
212 : : AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
213 : : AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
214 : : AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
215 : : AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
216 : : AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
217 : : AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
218 : : link offline */
219 : : AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
220 : : AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */
221 : : AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */
222 : : AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on
223 : : port start (wait until
224 : : error-handling stage) */
225 : : AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */
226 : : AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */
227 : :
228 : : #ifdef CONFIG_PCI_MSI
229 : : AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */
230 : : #else
231 : : /* compile out MSI infrastructure */
232 : : AHCI_HFLAG_MULTI_MSI = 0,
233 : : #endif
234 : : AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */
235 : : AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */
236 : : AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
237 : : only registers */
238 : : AHCI_HFLAG_IS_MOBILE = (1 << 25), /* mobile chipset, use
239 : : SATA_MOBILE_LPM_POLICY
240 : : as default lpm_policy */
241 : : AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
242 : : suspend/resume */
243 : :
244 : : /* ap->flags bits */
245 : :
246 : : AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
247 : : ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
248 : :
249 : : ICH_MAP = 0x90, /* ICH MAP register */
250 : : PCS_6 = 0x92, /* 6 port PCS */
251 : : PCS_7 = 0x94, /* 7+ port PCS (Denverton) */
252 : :
253 : : /* em constants */
254 : : EM_MAX_SLOTS = 8,
255 : : EM_MAX_RETRY = 5,
256 : :
257 : : /* em_ctl bits */
258 : : EM_CTL_RST = (1 << 9), /* Reset */
259 : : EM_CTL_TM = (1 << 8), /* Transmit Message */
260 : : EM_CTL_MR = (1 << 0), /* Message Received */
261 : : EM_CTL_ALHD = (1 << 26), /* Activity LED */
262 : : EM_CTL_XMT = (1 << 25), /* Transmit Only */
263 : : EM_CTL_SMB = (1 << 24), /* Single Message Buffer */
264 : : EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */
265 : : EM_CTL_SES = (1 << 18), /* SES-2 messages supported */
266 : : EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */
267 : : EM_CTL_LED = (1 << 16), /* LED messages supported */
268 : :
269 : : /* em message type */
270 : : EM_MSG_TYPE_LED = (1 << 0), /* LED */
271 : : EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */
272 : : EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */
273 : : EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */
274 : : };
275 : :
276 : : struct ahci_cmd_hdr {
277 : : __le32 opts;
278 : : __le32 status;
279 : : __le32 tbl_addr;
280 : : __le32 tbl_addr_hi;
281 : : __le32 reserved[4];
282 : : };
283 : :
284 : : struct ahci_sg {
285 : : __le32 addr;
286 : : __le32 addr_hi;
287 : : __le32 reserved;
288 : : __le32 flags_size;
289 : : };
290 : :
291 : : struct ahci_em_priv {
292 : : enum sw_activity blink_policy;
293 : : struct timer_list timer;
294 : : unsigned long saved_activity;
295 : : unsigned long activity;
296 : : unsigned long led_state;
297 : : struct ata_link *link;
298 : : };
299 : :
300 : : struct ahci_port_priv {
301 : : struct ata_link *active_link;
302 : : struct ahci_cmd_hdr *cmd_slot;
303 : : dma_addr_t cmd_slot_dma;
304 : : void *cmd_tbl;
305 : : dma_addr_t cmd_tbl_dma;
306 : : void *rx_fis;
307 : : dma_addr_t rx_fis_dma;
308 : : /* for NCQ spurious interrupt analysis */
309 : : unsigned int ncq_saw_d2h:1;
310 : : unsigned int ncq_saw_dmas:1;
311 : : unsigned int ncq_saw_sdb:1;
312 : : spinlock_t lock; /* protects parent ata_port */
313 : : u32 intr_mask; /* interrupts to enable */
314 : : bool fbs_supported; /* set iff FBS is supported */
315 : : bool fbs_enabled; /* set iff FBS is enabled */
316 : : int fbs_last_dev; /* save FBS.DEV of last FIS */
317 : : /* enclosure management info per PM slot */
318 : : struct ahci_em_priv em_priv[EM_MAX_SLOTS];
319 : : char *irq_desc; /* desc in /proc/interrupts */
320 : : };
321 : :
322 : : struct ahci_host_priv {
323 : : /* Input fields */
324 : : unsigned int flags; /* AHCI_HFLAG_* */
325 : : u32 force_port_map; /* force port map */
326 : : u32 mask_port_map; /* mask out particular bits */
327 : :
328 : : void __iomem * mmio; /* bus-independent mem map */
329 : : u32 cap; /* cap to use */
330 : : u32 cap2; /* cap2 to use */
331 : : u32 version; /* cached version */
332 : : u32 port_map; /* port map to use */
333 : : u32 saved_cap; /* saved initial cap */
334 : : u32 saved_cap2; /* saved initial cap2 */
335 : : u32 saved_port_map; /* saved initial port_map */
336 : : u32 em_loc; /* enclosure management location */
337 : : u32 em_buf_sz; /* EM buffer size in byte */
338 : : u32 em_msg_type; /* EM message type */
339 : : bool got_runtime_pm; /* Did we do pm_runtime_get? */
340 : : struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
341 : : struct reset_control *rsts; /* Optional */
342 : : struct regulator **target_pwrs; /* Optional */
343 : : struct regulator *ahci_regulator;/* Optional */
344 : : struct regulator *phy_regulator;/* Optional */
345 : : /*
346 : : * If platform uses PHYs. There is a 1:1 relation between the port number and
347 : : * the PHY position in this array.
348 : : */
349 : : struct phy **phys;
350 : : unsigned nports; /* Number of ports */
351 : : void *plat_data; /* Other platform data */
352 : : unsigned int irq; /* interrupt line */
353 : : /*
354 : : * Optional ahci_start_engine override, if not set this gets set to the
355 : : * default ahci_start_engine during ahci_save_initial_config, this can
356 : : * be overridden anytime before the host is activated.
357 : : */
358 : : void (*start_engine)(struct ata_port *ap);
359 : : /*
360 : : * Optional ahci_stop_engine override, if not set this gets set to the
361 : : * default ahci_stop_engine during ahci_save_initial_config, this can
362 : : * be overridden anytime before the host is activated.
363 : : */
364 : : int (*stop_engine)(struct ata_port *ap);
365 : :
366 : : irqreturn_t (*irq_handler)(int irq, void *dev_instance);
367 : :
368 : : /* only required for per-port MSI(-X) support */
369 : : int (*get_irq_vector)(struct ata_host *host,
370 : : int port);
371 : : };
372 : :
373 : : extern int ahci_ignore_sss;
374 : :
375 : : extern struct device_attribute *ahci_shost_attrs[];
376 : : extern struct device_attribute *ahci_sdev_attrs[];
377 : :
378 : : /*
379 : : * This must be instantiated by the edge drivers. Read the comments
380 : : * for ATA_BASE_SHT
381 : : */
382 : : #define AHCI_SHT(drv_name) \
383 : : ATA_NCQ_SHT(drv_name), \
384 : : .can_queue = AHCI_MAX_CMDS, \
385 : : .sg_tablesize = AHCI_MAX_SG, \
386 : : .dma_boundary = AHCI_DMA_BOUNDARY, \
387 : : .shost_attrs = ahci_shost_attrs, \
388 : : .sdev_attrs = ahci_sdev_attrs
389 : :
390 : : extern struct ata_port_operations ahci_ops;
391 : : extern struct ata_port_operations ahci_platform_ops;
392 : : extern struct ata_port_operations ahci_pmp_retry_srst_ops;
393 : :
394 : : unsigned int ahci_dev_classify(struct ata_port *ap);
395 : : void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
396 : : u32 opts);
397 : : void ahci_save_initial_config(struct device *dev,
398 : : struct ahci_host_priv *hpriv);
399 : : void ahci_init_controller(struct ata_host *host);
400 : : int ahci_reset_controller(struct ata_host *host);
401 : :
402 : : int ahci_do_softreset(struct ata_link *link, unsigned int *class,
403 : : int pmp, unsigned long deadline,
404 : : int (*check_ready)(struct ata_link *link));
405 : :
406 : : int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
407 : : unsigned long deadline, bool *online);
408 : :
409 : : unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
410 : : int ahci_stop_engine(struct ata_port *ap);
411 : : void ahci_start_fis_rx(struct ata_port *ap);
412 : : void ahci_start_engine(struct ata_port *ap);
413 : : int ahci_check_ready(struct ata_link *link);
414 : : int ahci_kick_engine(struct ata_port *ap);
415 : : int ahci_port_resume(struct ata_port *ap);
416 : : void ahci_set_em_messages(struct ahci_host_priv *hpriv,
417 : : struct ata_port_info *pi);
418 : : int ahci_reset_em(struct ata_host *host);
419 : : void ahci_print_info(struct ata_host *host, const char *scc_s);
420 : : int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
421 : : void ahci_error_handler(struct ata_port *ap);
422 : : u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
423 : :
424 : 0 : static inline void __iomem *__ahci_port_base(struct ata_host *host,
425 : : unsigned int port_no)
426 : : {
427 : 0 : struct ahci_host_priv *hpriv = host->private_data;
428 : 0 : void __iomem *mmio = hpriv->mmio;
429 : :
430 : 0 : return mmio + 0x100 + (port_no * 0x80);
431 : : }
432 : :
433 : 0 : static inline void __iomem *ahci_port_base(struct ata_port *ap)
434 : : {
435 [ # # # # : 0 : return __ahci_port_base(ap->host, ap->port_no);
# # # # #
# # # # #
# # # # #
# # # ]
436 : : }
437 : :
438 : 0 : static inline int ahci_nr_ports(u32 cap)
439 : : {
440 [ # # ]: 0 : return (cap & 0x1f) + 1;
441 : : }
442 : :
443 : : #endif /* _AHCI_H */
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