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1 : : /* SPDX-License-Identifier: GPL-2.0 */
2 : : /*
3 : : * pci.h
4 : : *
5 : : * PCI defines and function prototypes
6 : : * Copyright 1994, Drew Eckhardt
7 : : * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 : : *
9 : : * PCI Express ASPM defines and function prototypes
10 : : * Copyright (c) 2007 Intel Corp.
11 : : * Zhang Yanmin (yanmin.zhang@intel.com)
12 : : * Shaohua Li (shaohua.li@intel.com)
13 : : *
14 : : * For more information, please consult the following manuals (look at
15 : : * http://www.pcisig.com/ for how to get them):
16 : : *
17 : : * PCI BIOS Specification
18 : : * PCI Local Bus Specification
19 : : * PCI to PCI Bridge Specification
20 : : * PCI Express Specification
21 : : * PCI System Design Guide
22 : : */
23 : : #ifndef LINUX_PCI_H
24 : : #define LINUX_PCI_H
25 : :
26 : :
27 : : #include <linux/mod_devicetable.h>
28 : :
29 : : #include <linux/types.h>
30 : : #include <linux/init.h>
31 : : #include <linux/ioport.h>
32 : : #include <linux/list.h>
33 : : #include <linux/compiler.h>
34 : : #include <linux/errno.h>
35 : : #include <linux/kobject.h>
36 : : #include <linux/atomic.h>
37 : : #include <linux/device.h>
38 : : #include <linux/interrupt.h>
39 : : #include <linux/io.h>
40 : : #include <linux/resource_ext.h>
41 : : #include <uapi/linux/pci.h>
42 : :
43 : : #include <linux/pci_ids.h>
44 : :
45 : : /*
46 : : * The PCI interface treats multi-function devices as independent
47 : : * devices. The slot/function address of each device is encoded
48 : : * in a single byte as follows:
49 : : *
50 : : * 7:3 = slot
51 : : * 2:0 = function
52 : : *
53 : : * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
54 : : * In the interest of not exposing interfaces to user-space unnecessarily,
55 : : * the following kernel-only defines are being added here.
56 : : */
57 : : #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
58 : : /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
59 : : #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
60 : :
61 : : /* pci_slot represents a physical slot */
62 : : struct pci_slot {
63 : : struct pci_bus *bus; /* Bus this slot is on */
64 : : struct list_head list; /* Node in list of slots */
65 : : struct hotplug_slot *hotplug; /* Hotplug info (move here) */
66 : : unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
67 : : struct kobject kobj;
68 : : };
69 : :
70 : 609 : static inline const char *pci_slot_name(const struct pci_slot *slot)
71 : : {
72 [ # # ]: 609 : return kobject_name(&slot->kobj);
73 : : }
74 : :
75 : : /* File state for mmap()s on /proc/bus/pci/X/Y */
76 : : enum pci_mmap_state {
77 : : pci_mmap_io,
78 : : pci_mmap_mem
79 : : };
80 : :
81 : : /* For PCI devices, the region numbers are assigned this way: */
82 : : enum {
83 : : /* #0-5: standard PCI resources */
84 : : PCI_STD_RESOURCES,
85 : : PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
86 : :
87 : : /* #6: expansion ROM resource */
88 : : PCI_ROM_RESOURCE,
89 : :
90 : : /* Device-specific resources */
91 : : #ifdef CONFIG_PCI_IOV
92 : : PCI_IOV_RESOURCES,
93 : : PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
94 : : #endif
95 : :
96 : : /* Resources assigned to buses behind the bridge */
97 : : #define PCI_BRIDGE_RESOURCE_NUM 4
98 : :
99 : : PCI_BRIDGE_RESOURCES,
100 : : PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 : : PCI_BRIDGE_RESOURCE_NUM - 1,
102 : :
103 : : /* Total resources associated with a PCI device */
104 : : PCI_NUM_RESOURCES,
105 : :
106 : : /* Preserve this for compatibility */
107 : : DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
108 : : };
109 : :
110 : : /**
111 : : * enum pci_interrupt_pin - PCI INTx interrupt values
112 : : * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
113 : : * @PCI_INTERRUPT_INTA: PCI INTA pin
114 : : * @PCI_INTERRUPT_INTB: PCI INTB pin
115 : : * @PCI_INTERRUPT_INTC: PCI INTC pin
116 : : * @PCI_INTERRUPT_INTD: PCI INTD pin
117 : : *
118 : : * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
119 : : * PCI_INTERRUPT_PIN register.
120 : : */
121 : : enum pci_interrupt_pin {
122 : : PCI_INTERRUPT_UNKNOWN,
123 : : PCI_INTERRUPT_INTA,
124 : : PCI_INTERRUPT_INTB,
125 : : PCI_INTERRUPT_INTC,
126 : : PCI_INTERRUPT_INTD,
127 : : };
128 : :
129 : : /* The number of legacy PCI INTx interrupts */
130 : : #define PCI_NUM_INTX 4
131 : :
132 : : /*
133 : : * pci_power_t values must match the bits in the Capabilities PME_Support
134 : : * and Control/Status PowerState fields in the Power Management capability.
135 : : */
136 : : typedef int __bitwise pci_power_t;
137 : :
138 : : #define PCI_D0 ((pci_power_t __force) 0)
139 : : #define PCI_D1 ((pci_power_t __force) 1)
140 : : #define PCI_D2 ((pci_power_t __force) 2)
141 : : #define PCI_D3hot ((pci_power_t __force) 3)
142 : : #define PCI_D3cold ((pci_power_t __force) 4)
143 : : #define PCI_UNKNOWN ((pci_power_t __force) 5)
144 : : #define PCI_POWER_ERROR ((pci_power_t __force) -1)
145 : :
146 : : /* Remember to update this when the list above changes! */
147 : : extern const char *pci_power_names[];
148 : :
149 : 0 : static inline const char *pci_power_name(pci_power_t state)
150 : : {
151 : 0 : return pci_power_names[1 + (__force int) state];
152 : : }
153 : :
154 : : /**
155 : : * typedef pci_channel_state_t
156 : : *
157 : : * The pci_channel state describes connectivity between the CPU and
158 : : * the PCI device. If some PCI bus between here and the PCI device
159 : : * has crashed or locked up, this info is reflected here.
160 : : */
161 : : typedef unsigned int __bitwise pci_channel_state_t;
162 : :
163 : : enum pci_channel_state {
164 : : /* I/O channel is in normal state */
165 : : pci_channel_io_normal = (__force pci_channel_state_t) 1,
166 : :
167 : : /* I/O to channel is blocked */
168 : : pci_channel_io_frozen = (__force pci_channel_state_t) 2,
169 : :
170 : : /* PCI card is dead */
171 : : pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
172 : : };
173 : :
174 : : typedef unsigned int __bitwise pcie_reset_state_t;
175 : :
176 : : enum pcie_reset_state {
177 : : /* Reset is NOT asserted (Use to deassert reset) */
178 : : pcie_deassert_reset = (__force pcie_reset_state_t) 1,
179 : :
180 : : /* Use #PERST to reset PCIe device */
181 : : pcie_warm_reset = (__force pcie_reset_state_t) 2,
182 : :
183 : : /* Use PCIe Hot Reset to reset device */
184 : : pcie_hot_reset = (__force pcie_reset_state_t) 3
185 : : };
186 : :
187 : : typedef unsigned short __bitwise pci_dev_flags_t;
188 : : enum pci_dev_flags {
189 : : /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
190 : : PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
191 : : /* Device configuration is irrevocably lost if disabled into D3 */
192 : : PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
193 : : /* Provide indication device is assigned by a Virtual Machine Manager */
194 : : PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
195 : : /* Flag for quirk use to store if quirk-specific ACS is enabled */
196 : : PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
197 : : /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
198 : : PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
199 : : /* Do not use bus resets for device */
200 : : PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
201 : : /* Do not use PM reset even if device advertises NoSoftRst- */
202 : : PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
203 : : /* Get VPD from function 0 VPD */
204 : : PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
205 : : /* A non-root bridge where translation occurs, stop alias search here */
206 : : PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
207 : : /* Do not use FLR even if device advertises PCI_AF_CAP */
208 : : PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
209 : : /* Don't use Relaxed Ordering for TLPs directed at this device */
210 : : PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
211 : : };
212 : :
213 : : enum pci_irq_reroute_variant {
214 : : INTEL_IRQ_REROUTE_VARIANT = 1,
215 : : MAX_IRQ_REROUTE_VARIANTS = 3
216 : : };
217 : :
218 : : typedef unsigned short __bitwise pci_bus_flags_t;
219 : : enum pci_bus_flags {
220 : : PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
221 : : PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
222 : : PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
223 : : PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
224 : : };
225 : :
226 : : /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
227 : : enum pcie_link_width {
228 : : PCIE_LNK_WIDTH_RESRV = 0x00,
229 : : PCIE_LNK_X1 = 0x01,
230 : : PCIE_LNK_X2 = 0x02,
231 : : PCIE_LNK_X4 = 0x04,
232 : : PCIE_LNK_X8 = 0x08,
233 : : PCIE_LNK_X12 = 0x0c,
234 : : PCIE_LNK_X16 = 0x10,
235 : : PCIE_LNK_X32 = 0x20,
236 : : PCIE_LNK_WIDTH_UNKNOWN = 0xff,
237 : : };
238 : :
239 : : /* Based on the PCI Hotplug Spec, but some values are made up by us */
240 : : enum pci_bus_speed {
241 : : PCI_SPEED_33MHz = 0x00,
242 : : PCI_SPEED_66MHz = 0x01,
243 : : PCI_SPEED_66MHz_PCIX = 0x02,
244 : : PCI_SPEED_100MHz_PCIX = 0x03,
245 : : PCI_SPEED_133MHz_PCIX = 0x04,
246 : : PCI_SPEED_66MHz_PCIX_ECC = 0x05,
247 : : PCI_SPEED_100MHz_PCIX_ECC = 0x06,
248 : : PCI_SPEED_133MHz_PCIX_ECC = 0x07,
249 : : PCI_SPEED_66MHz_PCIX_266 = 0x09,
250 : : PCI_SPEED_100MHz_PCIX_266 = 0x0a,
251 : : PCI_SPEED_133MHz_PCIX_266 = 0x0b,
252 : : AGP_UNKNOWN = 0x0c,
253 : : AGP_1X = 0x0d,
254 : : AGP_2X = 0x0e,
255 : : AGP_4X = 0x0f,
256 : : AGP_8X = 0x10,
257 : : PCI_SPEED_66MHz_PCIX_533 = 0x11,
258 : : PCI_SPEED_100MHz_PCIX_533 = 0x12,
259 : : PCI_SPEED_133MHz_PCIX_533 = 0x13,
260 : : PCIE_SPEED_2_5GT = 0x14,
261 : : PCIE_SPEED_5_0GT = 0x15,
262 : : PCIE_SPEED_8_0GT = 0x16,
263 : : PCIE_SPEED_16_0GT = 0x17,
264 : : PCIE_SPEED_32_0GT = 0x18,
265 : : PCI_SPEED_UNKNOWN = 0xff,
266 : : };
267 : :
268 : : enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
269 : : enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
270 : :
271 : : struct pci_cap_saved_data {
272 : : u16 cap_nr;
273 : : bool cap_extended;
274 : : unsigned int size;
275 : : u32 data[0];
276 : : };
277 : :
278 : : struct pci_cap_saved_state {
279 : : struct hlist_node next;
280 : : struct pci_cap_saved_data cap;
281 : : };
282 : :
283 : : struct irq_affinity;
284 : : struct pcie_link_state;
285 : : struct pci_vpd;
286 : : struct pci_sriov;
287 : : struct pci_p2pdma;
288 : :
289 : : /* The pci_dev structure describes PCI devices */
290 : : struct pci_dev {
291 : : struct list_head bus_list; /* Node in per-bus list */
292 : : struct pci_bus *bus; /* Bus this device is on */
293 : : struct pci_bus *subordinate; /* Bus this device bridges to */
294 : :
295 : : void *sysdata; /* Hook for sys-specific extension */
296 : : struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
297 : : struct pci_slot *slot; /* Physical slot this device is in */
298 : :
299 : : unsigned int devfn; /* Encoded device & function index */
300 : : unsigned short vendor;
301 : : unsigned short device;
302 : : unsigned short subsystem_vendor;
303 : : unsigned short subsystem_device;
304 : : unsigned int class; /* 3 bytes: (base,sub,prog-if) */
305 : : u8 revision; /* PCI revision, low byte of class word */
306 : : u8 hdr_type; /* PCI header type (`multi' flag masked out) */
307 : : #ifdef CONFIG_PCIEAER
308 : : u16 aer_cap; /* AER capability offset */
309 : : struct aer_stats *aer_stats; /* AER stats for this device */
310 : : #endif
311 : : u8 pcie_cap; /* PCIe capability offset */
312 : : u8 msi_cap; /* MSI capability offset */
313 : : u8 msix_cap; /* MSI-X capability offset */
314 : : u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
315 : : u8 rom_base_reg; /* Config register controlling ROM */
316 : : u8 pin; /* Interrupt pin this device uses */
317 : : u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
318 : : unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
319 : :
320 : : struct pci_driver *driver; /* Driver bound to this device */
321 : : u64 dma_mask; /* Mask of the bits of bus address this
322 : : device implements. Normally this is
323 : : 0xffffffff. You only need to change
324 : : this if your device has broken DMA
325 : : or supports 64-bit transfers. */
326 : :
327 : : struct device_dma_parameters dma_parms;
328 : :
329 : : pci_power_t current_state; /* Current operating state. In ACPI,
330 : : this is D0-D3, D0 being fully
331 : : functional, and D3 being off. */
332 : : unsigned int imm_ready:1; /* Supports Immediate Readiness */
333 : : u8 pm_cap; /* PM capability offset */
334 : : unsigned int pme_support:5; /* Bitmask of states from which PME#
335 : : can be generated */
336 : : unsigned int pme_poll:1; /* Poll device's PME status bit */
337 : : unsigned int d1_support:1; /* Low power state D1 is supported */
338 : : unsigned int d2_support:1; /* Low power state D2 is supported */
339 : : unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
340 : : unsigned int no_d3cold:1; /* D3cold is forbidden */
341 : : unsigned int bridge_d3:1; /* Allow D3 for bridge */
342 : : unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
343 : : unsigned int mmio_always_on:1; /* Disallow turning off io/mem
344 : : decoding during BAR sizing */
345 : : unsigned int wakeup_prepared:1;
346 : : unsigned int runtime_d3cold:1; /* Whether go through runtime
347 : : D3cold, not set for devices
348 : : powered on/off by the
349 : : corresponding bridge */
350 : : unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
351 : : unsigned int ignore_hotplug:1; /* Ignore hotplug events */
352 : : unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
353 : : controlled exclusively by
354 : : user sysfs */
355 : : unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
356 : : bit manually */
357 : : unsigned int d3_delay; /* D3->D0 transition time in ms */
358 : : unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
359 : :
360 : : #ifdef CONFIG_PCIEASPM
361 : : struct pcie_link_state *link_state; /* ASPM link state */
362 : : unsigned int ltr_path:1; /* Latency Tolerance Reporting
363 : : supported from root to here */
364 : : #endif
365 : : unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
366 : :
367 : : pci_channel_state_t error_state; /* Current connectivity state */
368 : : struct device dev; /* Generic device interface */
369 : :
370 : : int cfg_size; /* Size of config space */
371 : :
372 : : /*
373 : : * Instead of touching interrupt line and base address registers
374 : : * directly, use the values stored here. They might be different!
375 : : */
376 : : unsigned int irq;
377 : : struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
378 : :
379 : : bool match_driver; /* Skip attaching driver */
380 : :
381 : : unsigned int transparent:1; /* Subtractive decode bridge */
382 : : unsigned int io_window:1; /* Bridge has I/O window */
383 : : unsigned int pref_window:1; /* Bridge has pref mem window */
384 : : unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
385 : : unsigned int multifunction:1; /* Multi-function device */
386 : :
387 : : unsigned int is_busmaster:1; /* Is busmaster */
388 : : unsigned int no_msi:1; /* May not use MSI */
389 : : unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
390 : : unsigned int block_cfg_access:1; /* Config space access blocked */
391 : : unsigned int broken_parity_status:1; /* Generates false positive parity */
392 : : unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
393 : : unsigned int msi_enabled:1;
394 : : unsigned int msix_enabled:1;
395 : : unsigned int ari_enabled:1; /* ARI forwarding */
396 : : unsigned int ats_enabled:1; /* Address Translation Svc */
397 : : unsigned int pasid_enabled:1; /* Process Address Space ID */
398 : : unsigned int pri_enabled:1; /* Page Request Interface */
399 : : unsigned int is_managed:1;
400 : : unsigned int needs_freset:1; /* Requires fundamental reset */
401 : : unsigned int state_saved:1;
402 : : unsigned int is_physfn:1;
403 : : unsigned int is_virtfn:1;
404 : : unsigned int reset_fn:1;
405 : : unsigned int is_hotplug_bridge:1;
406 : : unsigned int shpc_managed:1; /* SHPC owned by shpchp */
407 : : unsigned int is_thunderbolt:1; /* Thunderbolt controller */
408 : : /*
409 : : * Devices marked being untrusted are the ones that can potentially
410 : : * execute DMA attacks and similar. They are typically connected
411 : : * through external ports such as Thunderbolt but not limited to
412 : : * that. When an IOMMU is enabled they should be getting full
413 : : * mappings to make sure they cannot access arbitrary memory.
414 : : */
415 : : unsigned int untrusted:1;
416 : : unsigned int __aer_firmware_first_valid:1;
417 : : unsigned int __aer_firmware_first:1;
418 : : unsigned int broken_intx_masking:1; /* INTx masking can't be used */
419 : : unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
420 : : unsigned int irq_managed:1;
421 : : unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
422 : : unsigned int is_probed:1; /* Device probing in progress */
423 : : unsigned int link_active_reporting:1;/* Device capable of reporting link active */
424 : : unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
425 : : pci_dev_flags_t dev_flags;
426 : : atomic_t enable_cnt; /* pci_enable_device has been called */
427 : :
428 : : u32 saved_config_space[16]; /* Config space saved at suspend time */
429 : : struct hlist_head saved_cap_space;
430 : : struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
431 : : int rom_attr_enabled; /* Display of ROM attribute enabled? */
432 : : struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
433 : : struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
434 : :
435 : : #ifdef CONFIG_HOTPLUG_PCI_PCIE
436 : : unsigned int broken_cmd_compl:1; /* No compl for some cmds */
437 : : #endif
438 : : #ifdef CONFIG_PCIE_PTM
439 : : unsigned int ptm_root:1;
440 : : unsigned int ptm_enabled:1;
441 : : u8 ptm_granularity;
442 : : #endif
443 : : #ifdef CONFIG_PCI_MSI
444 : : const struct attribute_group **msi_irq_groups;
445 : : #endif
446 : : struct pci_vpd *vpd;
447 : : #ifdef CONFIG_PCI_ATS
448 : : union {
449 : : struct pci_sriov *sriov; /* PF: SR-IOV info */
450 : : struct pci_dev *physfn; /* VF: related PF */
451 : : };
452 : : u16 ats_cap; /* ATS Capability offset */
453 : : u8 ats_stu; /* ATS Smallest Translation Unit */
454 : : #endif
455 : : #ifdef CONFIG_PCI_PRI
456 : : u16 pri_cap; /* PRI Capability offset */
457 : : u32 pri_reqs_alloc; /* Number of PRI requests allocated */
458 : : unsigned int pasid_required:1; /* PRG Response PASID Required */
459 : : #endif
460 : : #ifdef CONFIG_PCI_PASID
461 : : u16 pasid_cap; /* PASID Capability offset */
462 : : u16 pasid_features;
463 : : #endif
464 : : #ifdef CONFIG_PCI_P2PDMA
465 : : struct pci_p2pdma *p2pdma;
466 : : #endif
467 : : phys_addr_t rom; /* Physical address if not from BAR */
468 : : size_t romlen; /* Length if not from BAR */
469 : : char *driver_override; /* Driver name to force a match */
470 : :
471 : : unsigned long priv_flags; /* Private flags for the PCI driver */
472 : : };
473 : :
474 : 609 : static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
475 : : {
476 : : #ifdef CONFIG_PCI_IOV
477 : : if (dev->is_virtfn)
478 : : dev = dev->physfn;
479 : : #endif
480 [ # # # # : 609 : return dev;
# # ]
481 : : }
482 : :
483 : : struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
484 : :
485 : : #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
486 : : #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
487 : :
488 : 0 : static inline int pci_channel_offline(struct pci_dev *pdev)
489 : : {
490 [ # # # # : 0 : return (pdev->error_state != pci_channel_io_normal);
# # # # #
# # # #
# ]
491 : : }
492 : :
493 : : struct pci_host_bridge {
494 : : struct device dev;
495 : : struct pci_bus *bus; /* Root bus */
496 : : struct pci_ops *ops;
497 : : void *sysdata;
498 : : int busnr;
499 : : struct list_head windows; /* resource_entry */
500 : : struct list_head dma_ranges; /* dma ranges resource list */
501 : : u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
502 : : int (*map_irq)(const struct pci_dev *, u8, u8);
503 : : void (*release_fn)(struct pci_host_bridge *);
504 : : void *release_data;
505 : : struct msi_controller *msi;
506 : : unsigned int ignore_reset_delay:1; /* For entire hierarchy */
507 : : unsigned int no_ext_tags:1; /* No Extended Tags */
508 : : unsigned int native_aer:1; /* OS may use PCIe AER */
509 : : unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
510 : : unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
511 : : unsigned int native_pme:1; /* OS may use PCIe PME */
512 : : unsigned int native_ltr:1; /* OS may use PCIe LTR */
513 : : unsigned int preserve_config:1; /* Preserve FW resource setup */
514 : :
515 : : /* Resource alignment requirements */
516 : : resource_size_t (*align_resource)(struct pci_dev *dev,
517 : : const struct resource *res,
518 : : resource_size_t start,
519 : : resource_size_t size,
520 : : resource_size_t align);
521 : : unsigned long private[0] ____cacheline_aligned;
522 : : };
523 : :
524 : : #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
525 : :
526 : : static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
527 : : {
528 : : return (void *)bridge->private;
529 : : }
530 : :
531 : : static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
532 : : {
533 : : return container_of(priv, struct pci_host_bridge, private);
534 : : }
535 : :
536 : : struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
537 : : struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
538 : : size_t priv);
539 : : void pci_free_host_bridge(struct pci_host_bridge *bridge);
540 : : struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
541 : :
542 : : void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
543 : : void (*release_fn)(struct pci_host_bridge *),
544 : : void *release_data);
545 : :
546 : : int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
547 : :
548 : : /*
549 : : * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
550 : : * to P2P or CardBus bridge windows) go in a table. Additional ones (for
551 : : * buses below host bridges or subtractive decode bridges) go in the list.
552 : : * Use pci_bus_for_each_resource() to iterate through all the resources.
553 : : */
554 : :
555 : : /*
556 : : * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
557 : : * and there's no way to program the bridge with the details of the window.
558 : : * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
559 : : * decode bit set, because they are explicit and can be programmed with _SRS.
560 : : */
561 : : #define PCI_SUBTRACTIVE_DECODE 0x1
562 : :
563 : : struct pci_bus_resource {
564 : : struct list_head list;
565 : : struct resource *res;
566 : : unsigned int flags;
567 : : };
568 : :
569 : : #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
570 : :
571 : : struct pci_bus {
572 : : struct list_head node; /* Node in list of buses */
573 : : struct pci_bus *parent; /* Parent bus this bridge is on */
574 : : struct list_head children; /* List of child buses */
575 : : struct list_head devices; /* List of devices on this bus */
576 : : struct pci_dev *self; /* Bridge device as seen by parent */
577 : : struct list_head slots; /* List of slots on this bus;
578 : : protected by pci_slot_mutex */
579 : : struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
580 : : struct list_head resources; /* Address space routed to this bus */
581 : : struct resource busn_res; /* Bus numbers routed to this bus */
582 : :
583 : : struct pci_ops *ops; /* Configuration access functions */
584 : : struct msi_controller *msi; /* MSI controller */
585 : : void *sysdata; /* Hook for sys-specific extension */
586 : : struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
587 : :
588 : : unsigned char number; /* Bus number */
589 : : unsigned char primary; /* Number of primary bridge */
590 : : unsigned char max_bus_speed; /* enum pci_bus_speed */
591 : : unsigned char cur_bus_speed; /* enum pci_bus_speed */
592 : : #ifdef CONFIG_PCI_DOMAINS_GENERIC
593 : : int domain_nr;
594 : : #endif
595 : :
596 : : char name[48];
597 : :
598 : : unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
599 : : pci_bus_flags_t bus_flags; /* Inherited by child buses */
600 : : struct device *bridge;
601 : : struct device dev;
602 : : struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
603 : : struct bin_attribute *legacy_mem; /* Legacy mem */
604 : : unsigned int is_added:1;
605 : : };
606 : :
607 : : #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
608 : :
609 : 315 : static inline u16 pci_dev_id(struct pci_dev *dev)
610 : : {
611 [ # # # # ]: 315 : return PCI_DEVID(dev->bus->number, dev->devfn);
612 : : }
613 : :
614 : : /*
615 : : * Returns true if the PCI bus is root (behind host-PCI bridge),
616 : : * false otherwise
617 : : *
618 : : * Some code assumes that "bus->self == NULL" means that bus is a root bus.
619 : : * This is incorrect because "virtual" buses added for SR-IOV (via
620 : : * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
621 : : */
622 : 1827 : static inline bool pci_is_root_bus(struct pci_bus *pbus)
623 : : {
624 [ + + + + : 1218 : return !(pbus->parent);
- + - + ]
625 : : }
626 : :
627 : : /**
628 : : * pci_is_bridge - check if the PCI device is a bridge
629 : : * @dev: PCI device
630 : : *
631 : : * Return true if the PCI device is bridge whether it has subordinate
632 : : * or not.
633 : : */
634 : 882 : static inline bool pci_is_bridge(struct pci_dev *dev)
635 : : {
636 [ - + - + : 882 : return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
- + # # #
# # # ]
637 : : dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
638 : : }
639 : :
640 : : #define for_each_pci_bridge(dev, bus) \
641 : : list_for_each_entry(dev, &bus->devices, bus_list) \
642 : : if (!pci_is_bridge(dev)) {} else
643 : :
644 : 609 : static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
645 : : {
646 : 609 : dev = pci_physfn(dev);
647 [ - - - + : 609 : if (pci_is_root_bus(dev->bus))
- + - + -
+ - - - -
- - ]
648 : : return NULL;
649 : :
650 [ # # # # : 0 : return dev->bus->self;
# # # # #
# # # #
# ]
651 : : }
652 : :
653 : : #ifdef CONFIG_PCI_MSI
654 : 105 : static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
655 : : {
656 [ - - + - : 105 : return pci_dev->msi_enabled || pci_dev->msix_enabled;
+ - ]
657 : : }
658 : : #else
659 : : static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
660 : : #endif
661 : :
662 : : /* Error values that may be returned by PCI functions */
663 : : #define PCIBIOS_SUCCESSFUL 0x00
664 : : #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
665 : : #define PCIBIOS_BAD_VENDOR_ID 0x83
666 : : #define PCIBIOS_DEVICE_NOT_FOUND 0x86
667 : : #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
668 : : #define PCIBIOS_SET_FAILED 0x88
669 : : #define PCIBIOS_BUFFER_TOO_SMALL 0x89
670 : :
671 : : /* Translate above to generic errno for passing back through non-PCI code */
672 : 672 : static inline int pcibios_err_to_errno(int err)
673 : : {
674 [ - - - - : 672 : if (err <= PCIBIOS_SUCCESSFUL)
- - - + -
- - - ]
675 : : return err; /* Assume already errno */
676 : :
677 [ # # # # : 0 : switch (err) {
# # # # #
# # # ]
678 : : case PCIBIOS_FUNC_NOT_SUPPORTED:
679 : : return -ENOENT;
680 : : case PCIBIOS_BAD_VENDOR_ID:
681 : : return -ENOTTY;
682 : : case PCIBIOS_DEVICE_NOT_FOUND:
683 : : return -ENODEV;
684 : : case PCIBIOS_BAD_REGISTER_NUMBER:
685 : : return -EFAULT;
686 : : case PCIBIOS_SET_FAILED:
687 : : return -EIO;
688 : : case PCIBIOS_BUFFER_TOO_SMALL:
689 : : return -ENOSPC;
690 : : }
691 : :
692 : : return -ERANGE;
693 : : }
694 : :
695 : : /* Low-level architecture-dependent routines */
696 : :
697 : : struct pci_ops {
698 : : int (*add_bus)(struct pci_bus *bus);
699 : : void (*remove_bus)(struct pci_bus *bus);
700 : : void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
701 : : int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
702 : : int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
703 : : };
704 : :
705 : : /*
706 : : * ACPI needs to be able to access PCI config space before we've done a
707 : : * PCI bus scan and created pci_bus structures.
708 : : */
709 : : int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
710 : : int reg, int len, u32 *val);
711 : : int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
712 : : int reg, int len, u32 val);
713 : :
714 : : #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
715 : : typedef u64 pci_bus_addr_t;
716 : : #else
717 : : typedef u32 pci_bus_addr_t;
718 : : #endif
719 : :
720 : : struct pci_bus_region {
721 : : pci_bus_addr_t start;
722 : : pci_bus_addr_t end;
723 : : };
724 : :
725 : : struct pci_dynids {
726 : : spinlock_t lock; /* Protects list, index */
727 : : struct list_head list; /* For IDs added at runtime */
728 : : };
729 : :
730 : :
731 : : /*
732 : : * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
733 : : * a set of callbacks in struct pci_error_handlers, that device driver
734 : : * will be notified of PCI bus errors, and will be driven to recovery
735 : : * when an error occurs.
736 : : */
737 : :
738 : : typedef unsigned int __bitwise pci_ers_result_t;
739 : :
740 : : enum pci_ers_result {
741 : : /* No result/none/not supported in device driver */
742 : : PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
743 : :
744 : : /* Device driver can recover without slot reset */
745 : : PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
746 : :
747 : : /* Device driver wants slot to be reset */
748 : : PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
749 : :
750 : : /* Device has completely failed, is unrecoverable */
751 : : PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
752 : :
753 : : /* Device driver is fully recovered and operational */
754 : : PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
755 : :
756 : : /* No AER capabilities registered for the driver */
757 : : PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
758 : : };
759 : :
760 : : /* PCI bus error event callbacks */
761 : : struct pci_error_handlers {
762 : : /* PCI bus error detected on this device */
763 : : pci_ers_result_t (*error_detected)(struct pci_dev *dev,
764 : : enum pci_channel_state error);
765 : :
766 : : /* MMIO has been re-enabled, but not DMA */
767 : : pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
768 : :
769 : : /* PCI slot has been reset */
770 : : pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
771 : :
772 : : /* PCI function reset prepare or completed */
773 : : void (*reset_prepare)(struct pci_dev *dev);
774 : : void (*reset_done)(struct pci_dev *dev);
775 : :
776 : : /* Device driver may resume normal operations */
777 : : void (*resume)(struct pci_dev *dev);
778 : : };
779 : :
780 : :
781 : : struct module;
782 : :
783 : : /**
784 : : * struct pci_driver - PCI driver structure
785 : : * @node: List of driver structures.
786 : : * @name: Driver name.
787 : : * @id_table: Pointer to table of device IDs the driver is
788 : : * interested in. Most drivers should export this
789 : : * table using MODULE_DEVICE_TABLE(pci,...).
790 : : * @probe: This probing function gets called (during execution
791 : : * of pci_register_driver() for already existing
792 : : * devices or later if a new device gets inserted) for
793 : : * all PCI devices which match the ID table and are not
794 : : * "owned" by the other drivers yet. This function gets
795 : : * passed a "struct pci_dev \*" for each device whose
796 : : * entry in the ID table matches the device. The probe
797 : : * function returns zero when the driver chooses to
798 : : * take "ownership" of the device or an error code
799 : : * (negative number) otherwise.
800 : : * The probe function always gets called from process
801 : : * context, so it can sleep.
802 : : * @remove: The remove() function gets called whenever a device
803 : : * being handled by this driver is removed (either during
804 : : * deregistration of the driver or when it's manually
805 : : * pulled out of a hot-pluggable slot).
806 : : * The remove function always gets called from process
807 : : * context, so it can sleep.
808 : : * @suspend: Put device into low power state.
809 : : * @resume: Wake device from low power state.
810 : : * (Please see Documentation/power/pci.rst for descriptions
811 : : * of PCI Power Management and the related functions.)
812 : : * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
813 : : * Intended to stop any idling DMA operations.
814 : : * Useful for enabling wake-on-lan (NIC) or changing
815 : : * the power state of a device before reboot.
816 : : * e.g. drivers/net/e100.c.
817 : : * @sriov_configure: Optional driver callback to allow configuration of
818 : : * number of VFs to enable via sysfs "sriov_numvfs" file.
819 : : * @err_handler: See Documentation/PCI/pci-error-recovery.rst
820 : : * @groups: Sysfs attribute groups.
821 : : * @driver: Driver model structure.
822 : : * @dynids: List of dynamically added device IDs.
823 : : */
824 : : struct pci_driver {
825 : : struct list_head node;
826 : : const char *name;
827 : : const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
828 : : int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
829 : : void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
830 : : int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
831 : : int (*resume)(struct pci_dev *dev); /* Device woken up */
832 : : void (*shutdown)(struct pci_dev *dev);
833 : : int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
834 : : const struct pci_error_handlers *err_handler;
835 : : const struct attribute_group **groups;
836 : : struct device_driver driver;
837 : : struct pci_dynids dynids;
838 : : };
839 : :
840 : : #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
841 : :
842 : : /**
843 : : * PCI_DEVICE - macro used to describe a specific PCI device
844 : : * @vend: the 16 bit PCI Vendor ID
845 : : * @dev: the 16 bit PCI Device ID
846 : : *
847 : : * This macro is used to create a struct pci_device_id that matches a
848 : : * specific device. The subvendor and subdevice fields will be set to
849 : : * PCI_ANY_ID.
850 : : */
851 : : #define PCI_DEVICE(vend,dev) \
852 : : .vendor = (vend), .device = (dev), \
853 : : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
854 : :
855 : : /**
856 : : * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
857 : : * @vend: the 16 bit PCI Vendor ID
858 : : * @dev: the 16 bit PCI Device ID
859 : : * @subvend: the 16 bit PCI Subvendor ID
860 : : * @subdev: the 16 bit PCI Subdevice ID
861 : : *
862 : : * This macro is used to create a struct pci_device_id that matches a
863 : : * specific device with subsystem information.
864 : : */
865 : : #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
866 : : .vendor = (vend), .device = (dev), \
867 : : .subvendor = (subvend), .subdevice = (subdev)
868 : :
869 : : /**
870 : : * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
871 : : * @dev_class: the class, subclass, prog-if triple for this device
872 : : * @dev_class_mask: the class mask for this device
873 : : *
874 : : * This macro is used to create a struct pci_device_id that matches a
875 : : * specific PCI class. The vendor, device, subvendor, and subdevice
876 : : * fields will be set to PCI_ANY_ID.
877 : : */
878 : : #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
879 : : .class = (dev_class), .class_mask = (dev_class_mask), \
880 : : .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
881 : : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
882 : :
883 : : /**
884 : : * PCI_VDEVICE - macro used to describe a specific PCI device in short form
885 : : * @vend: the vendor name
886 : : * @dev: the 16 bit PCI Device ID
887 : : *
888 : : * This macro is used to create a struct pci_device_id that matches a
889 : : * specific PCI device. The subvendor, and subdevice fields will be set
890 : : * to PCI_ANY_ID. The macro allows the next field to follow as the device
891 : : * private data.
892 : : */
893 : : #define PCI_VDEVICE(vend, dev) \
894 : : .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
895 : : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
896 : :
897 : : /**
898 : : * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
899 : : * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
900 : : * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
901 : : * @data: the driver data to be filled
902 : : *
903 : : * This macro is used to create a struct pci_device_id that matches a
904 : : * specific PCI device. The subvendor, and subdevice fields will be set
905 : : * to PCI_ANY_ID.
906 : : */
907 : : #define PCI_DEVICE_DATA(vend, dev, data) \
908 : : .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
909 : : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
910 : : .driver_data = (kernel_ulong_t)(data)
911 : :
912 : : enum {
913 : : PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
914 : : PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
915 : : PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
916 : : PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
917 : : PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
918 : : PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
919 : : PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
920 : : };
921 : :
922 : : #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
923 : : #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
924 : : #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
925 : : #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
926 : :
927 : : /* These external functions are only available when PCI support is enabled */
928 : : #ifdef CONFIG_PCI
929 : :
930 : : extern unsigned int pci_flags;
931 : :
932 : : static inline void pci_set_flags(int flags) { pci_flags = flags; }
933 : 0 : static inline void pci_add_flags(int flags) { pci_flags |= flags; }
934 : : static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
935 [ # # ]: 0 : static inline int pci_has_flag(int flag) { return pci_flags & flag; }
936 : :
937 : : void pcie_bus_configure_settings(struct pci_bus *bus);
938 : :
939 : : enum pcie_bus_config_types {
940 : : PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
941 : : PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
942 : : PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
943 : : PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
944 : : PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
945 : : };
946 : :
947 : : extern enum pcie_bus_config_types pcie_bus_config;
948 : :
949 : : extern struct bus_type pci_bus_type;
950 : :
951 : : /* Do NOT directly access these two variables, unless you are arch-specific PCI
952 : : * code, or PCI core code. */
953 : : extern struct list_head pci_root_buses; /* List of all known PCI buses */
954 : : /* Some device drivers need know if PCI is initiated */
955 : : int no_pci_devices(void);
956 : :
957 : : void pcibios_resource_survey_bus(struct pci_bus *bus);
958 : : void pcibios_bus_add_device(struct pci_dev *pdev);
959 : : void pcibios_add_bus(struct pci_bus *bus);
960 : : void pcibios_remove_bus(struct pci_bus *bus);
961 : : void pcibios_fixup_bus(struct pci_bus *);
962 : : int __must_check pcibios_enable_device(struct pci_dev *, int mask);
963 : : /* Architecture-specific versions may override this (weak) */
964 : : char *pcibios_setup(char *str);
965 : :
966 : : /* Used only when drivers/pci/setup.c is used */
967 : : resource_size_t pcibios_align_resource(void *, const struct resource *,
968 : : resource_size_t,
969 : : resource_size_t);
970 : :
971 : : /* Weak but can be overridden by arch */
972 : : void pci_fixup_cardbus(struct pci_bus *);
973 : :
974 : : /* Generic PCI functions used internally */
975 : :
976 : : void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
977 : : struct resource *res);
978 : : void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
979 : : struct pci_bus_region *region);
980 : : void pcibios_scan_specific_bus(int busn);
981 : : struct pci_bus *pci_find_bus(int domain, int busnr);
982 : : void pci_bus_add_devices(const struct pci_bus *bus);
983 : : struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
984 : : struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
985 : : struct pci_ops *ops, void *sysdata,
986 : : struct list_head *resources);
987 : : int pci_host_probe(struct pci_host_bridge *bridge);
988 : : int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
989 : : int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
990 : : void pci_bus_release_busn_res(struct pci_bus *b);
991 : : struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
992 : : struct pci_ops *ops, void *sysdata,
993 : : struct list_head *resources);
994 : : int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
995 : : struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
996 : : int busnr);
997 : : struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
998 : : const char *name,
999 : : struct hotplug_slot *hotplug);
1000 : : void pci_destroy_slot(struct pci_slot *slot);
1001 : : #ifdef CONFIG_SYSFS
1002 : : void pci_dev_assign_slot(struct pci_dev *dev);
1003 : : #else
1004 : : static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1005 : : #endif
1006 : : int pci_scan_slot(struct pci_bus *bus, int devfn);
1007 : : struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1008 : : void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1009 : : unsigned int pci_scan_child_bus(struct pci_bus *bus);
1010 : : void pci_bus_add_device(struct pci_dev *dev);
1011 : : void pci_read_bridge_bases(struct pci_bus *child);
1012 : : struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1013 : : struct resource *res);
1014 : : struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
1015 : : u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1016 : : int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1017 : : u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1018 : : struct pci_dev *pci_dev_get(struct pci_dev *dev);
1019 : : void pci_dev_put(struct pci_dev *dev);
1020 : : void pci_remove_bus(struct pci_bus *b);
1021 : : void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1022 : : void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1023 : : void pci_stop_root_bus(struct pci_bus *bus);
1024 : : void pci_remove_root_bus(struct pci_bus *bus);
1025 : : void pci_setup_cardbus(struct pci_bus *bus);
1026 : : void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1027 : : void pci_sort_breadthfirst(void);
1028 : : #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1029 : : #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1030 : :
1031 : : /* Generic PCI functions exported to card drivers */
1032 : :
1033 : : enum pci_lost_interrupt_reason {
1034 : : PCI_LOST_IRQ_NO_INFORMATION = 0,
1035 : : PCI_LOST_IRQ_DISABLE_MSI,
1036 : : PCI_LOST_IRQ_DISABLE_MSIX,
1037 : : PCI_LOST_IRQ_DISABLE_ACPI,
1038 : : };
1039 : : enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
1040 : : int pci_find_capability(struct pci_dev *dev, int cap);
1041 : : int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1042 : : int pci_find_ext_capability(struct pci_dev *dev, int cap);
1043 : : int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1044 : : int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1045 : : int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1046 : : struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1047 : :
1048 : : struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1049 : : struct pci_dev *from);
1050 : : struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1051 : : unsigned int ss_vendor, unsigned int ss_device,
1052 : : struct pci_dev *from);
1053 : : struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1054 : : struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1055 : : unsigned int devfn);
1056 : : struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1057 : : int pci_dev_present(const struct pci_device_id *ids);
1058 : :
1059 : : int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1060 : : int where, u8 *val);
1061 : : int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1062 : : int where, u16 *val);
1063 : : int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1064 : : int where, u32 *val);
1065 : : int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1066 : : int where, u8 val);
1067 : : int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1068 : : int where, u16 val);
1069 : : int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1070 : : int where, u32 val);
1071 : :
1072 : : int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1073 : : int where, int size, u32 *val);
1074 : : int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1075 : : int where, int size, u32 val);
1076 : : int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1077 : : int where, int size, u32 *val);
1078 : : int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1079 : : int where, int size, u32 val);
1080 : :
1081 : : struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1082 : :
1083 : : int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1084 : : int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1085 : : int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1086 : : int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1087 : : int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1088 : : int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1089 : :
1090 : : int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1091 : : int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1092 : : int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1093 : : int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1094 : : int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1095 : : u16 clear, u16 set);
1096 : : int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1097 : : u32 clear, u32 set);
1098 : :
1099 : 0 : static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1100 : : u16 set)
1101 : : {
1102 : 0 : return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1103 : : }
1104 : :
1105 : 0 : static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1106 : : u32 set)
1107 : : {
1108 : 0 : return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1109 : : }
1110 : :
1111 : 0 : static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1112 : : u16 clear)
1113 : : {
1114 : 0 : return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1115 : : }
1116 : :
1117 : : static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1118 : : u32 clear)
1119 : : {
1120 : : return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1121 : : }
1122 : :
1123 : : /* User-space driven config access */
1124 : : int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1125 : : int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1126 : : int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1127 : : int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1128 : : int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1129 : : int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1130 : :
1131 : : int __must_check pci_enable_device(struct pci_dev *dev);
1132 : : int __must_check pci_enable_device_io(struct pci_dev *dev);
1133 : : int __must_check pci_enable_device_mem(struct pci_dev *dev);
1134 : : int __must_check pci_reenable_device(struct pci_dev *);
1135 : : int __must_check pcim_enable_device(struct pci_dev *pdev);
1136 : : void pcim_pin_device(struct pci_dev *pdev);
1137 : :
1138 : : static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1139 : : {
1140 : : /*
1141 : : * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1142 : : * writable and no quirk has marked the feature broken.
1143 : : */
1144 : : return !pdev->broken_intx_masking;
1145 : : }
1146 : :
1147 : 0 : static inline int pci_is_enabled(struct pci_dev *pdev)
1148 : : {
1149 : 0 : return (atomic_read(&pdev->enable_cnt) > 0);
1150 : : }
1151 : :
1152 : 147 : static inline int pci_is_managed(struct pci_dev *pdev)
1153 : : {
1154 [ - - - - : 147 : return pdev->is_managed;
+ + - - +
- - - ]
1155 : : }
1156 : :
1157 : : void pci_disable_device(struct pci_dev *dev);
1158 : :
1159 : : extern unsigned int pcibios_max_latency;
1160 : : void pci_set_master(struct pci_dev *dev);
1161 : : void pci_clear_master(struct pci_dev *dev);
1162 : :
1163 : : int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1164 : : int pci_set_cacheline_size(struct pci_dev *dev);
1165 : : #define HAVE_PCI_SET_MWI
1166 : : int __must_check pci_set_mwi(struct pci_dev *dev);
1167 : : int __must_check pcim_set_mwi(struct pci_dev *dev);
1168 : : int pci_try_set_mwi(struct pci_dev *dev);
1169 : : void pci_clear_mwi(struct pci_dev *dev);
1170 : : void pci_intx(struct pci_dev *dev, int enable);
1171 : : bool pci_check_and_mask_intx(struct pci_dev *dev);
1172 : : bool pci_check_and_unmask_intx(struct pci_dev *dev);
1173 : : int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1174 : : int pci_wait_for_pending_transaction(struct pci_dev *dev);
1175 : : int pcix_get_max_mmrbc(struct pci_dev *dev);
1176 : : int pcix_get_mmrbc(struct pci_dev *dev);
1177 : : int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1178 : : int pcie_get_readrq(struct pci_dev *dev);
1179 : : int pcie_set_readrq(struct pci_dev *dev, int rq);
1180 : : int pcie_get_mps(struct pci_dev *dev);
1181 : : int pcie_set_mps(struct pci_dev *dev, int mps);
1182 : : u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1183 : : enum pci_bus_speed *speed,
1184 : : enum pcie_link_width *width);
1185 : : void pcie_print_link_status(struct pci_dev *dev);
1186 : : bool pcie_has_flr(struct pci_dev *dev);
1187 : : int pcie_flr(struct pci_dev *dev);
1188 : : int __pci_reset_function_locked(struct pci_dev *dev);
1189 : : int pci_reset_function(struct pci_dev *dev);
1190 : : int pci_reset_function_locked(struct pci_dev *dev);
1191 : : int pci_try_reset_function(struct pci_dev *dev);
1192 : : int pci_probe_reset_slot(struct pci_slot *slot);
1193 : : int pci_probe_reset_bus(struct pci_bus *bus);
1194 : : int pci_reset_bus(struct pci_dev *dev);
1195 : : void pci_reset_secondary_bus(struct pci_dev *dev);
1196 : : void pcibios_reset_secondary_bus(struct pci_dev *dev);
1197 : : void pci_update_resource(struct pci_dev *dev, int resno);
1198 : : int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1199 : : int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1200 : : void pci_release_resource(struct pci_dev *dev, int resno);
1201 : : int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1202 : : int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1203 : : bool pci_device_is_present(struct pci_dev *pdev);
1204 : : void pci_ignore_hotplug(struct pci_dev *dev);
1205 : : struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1206 : :
1207 : : int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1208 : : irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1209 : : const char *fmt, ...);
1210 : : void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1211 : :
1212 : : /* ROM control related routines */
1213 : : int pci_enable_rom(struct pci_dev *pdev);
1214 : : void pci_disable_rom(struct pci_dev *pdev);
1215 : : void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1216 : : void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1217 : : void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1218 : :
1219 : : /* Power management related routines */
1220 : : int pci_save_state(struct pci_dev *dev);
1221 : : void pci_restore_state(struct pci_dev *dev);
1222 : : struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1223 : : int pci_load_saved_state(struct pci_dev *dev,
1224 : : struct pci_saved_state *state);
1225 : : int pci_load_and_free_saved_state(struct pci_dev *dev,
1226 : : struct pci_saved_state **state);
1227 : : struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1228 : : struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1229 : : u16 cap);
1230 : : int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1231 : : int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1232 : : u16 cap, unsigned int size);
1233 : : int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1234 : : int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1235 : : pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1236 : : bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1237 : : void pci_pme_active(struct pci_dev *dev, bool enable);
1238 : : int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1239 : : int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1240 : : int pci_prepare_to_sleep(struct pci_dev *dev);
1241 : : int pci_back_from_sleep(struct pci_dev *dev);
1242 : : bool pci_dev_run_wake(struct pci_dev *dev);
1243 : : void pci_d3cold_enable(struct pci_dev *dev);
1244 : : void pci_d3cold_disable(struct pci_dev *dev);
1245 : : bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1246 : : void pci_wakeup_bus(struct pci_bus *bus);
1247 : : void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1248 : :
1249 : : /* For use by arch with custom probe code */
1250 : : void set_pcie_port_type(struct pci_dev *pdev);
1251 : : void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1252 : :
1253 : : /* Functions for PCI Hotplug drivers to use */
1254 : : int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1255 : : unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1256 : : unsigned int pci_rescan_bus(struct pci_bus *bus);
1257 : : void pci_lock_rescan_remove(void);
1258 : : void pci_unlock_rescan_remove(void);
1259 : :
1260 : : /* Vital Product Data routines */
1261 : : ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1262 : : ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1263 : : int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1264 : :
1265 : : /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1266 : : resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1267 : : void pci_bus_assign_resources(const struct pci_bus *bus);
1268 : : void pci_bus_claim_resources(struct pci_bus *bus);
1269 : : void pci_bus_size_bridges(struct pci_bus *bus);
1270 : : int pci_claim_resource(struct pci_dev *, int);
1271 : : int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1272 : : void pci_assign_unassigned_resources(void);
1273 : : void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1274 : : void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1275 : : void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1276 : : int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1277 : : void pdev_enable_device(struct pci_dev *);
1278 : : int pci_enable_resources(struct pci_dev *, int mask);
1279 : : void pci_assign_irq(struct pci_dev *dev);
1280 : : struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1281 : : #define HAVE_PCI_REQ_REGIONS 2
1282 : : int __must_check pci_request_regions(struct pci_dev *, const char *);
1283 : : int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1284 : : void pci_release_regions(struct pci_dev *);
1285 : : int __must_check pci_request_region(struct pci_dev *, int, const char *);
1286 : : void pci_release_region(struct pci_dev *, int);
1287 : : int pci_request_selected_regions(struct pci_dev *, int, const char *);
1288 : : int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1289 : : void pci_release_selected_regions(struct pci_dev *, int);
1290 : :
1291 : : /* drivers/pci/bus.c */
1292 : : void pci_add_resource(struct list_head *resources, struct resource *res);
1293 : : void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1294 : : resource_size_t offset);
1295 : : void pci_free_resource_list(struct list_head *resources);
1296 : : void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1297 : : unsigned int flags);
1298 : : struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1299 : : void pci_bus_remove_resources(struct pci_bus *bus);
1300 : : int devm_request_pci_bus_resources(struct device *dev,
1301 : : struct list_head *resources);
1302 : :
1303 : : /* Temporary until new and working PCI SBR API in place */
1304 : : int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1305 : :
1306 : : #define pci_bus_for_each_resource(bus, res, i) \
1307 : : for (i = 0; \
1308 : : (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1309 : : i++)
1310 : :
1311 : : int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1312 : : struct resource *res, resource_size_t size,
1313 : : resource_size_t align, resource_size_t min,
1314 : : unsigned long type_mask,
1315 : : resource_size_t (*alignf)(void *,
1316 : : const struct resource *,
1317 : : resource_size_t,
1318 : : resource_size_t),
1319 : : void *alignf_data);
1320 : :
1321 : :
1322 : : int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1323 : : resource_size_t size);
1324 : : unsigned long pci_address_to_pio(phys_addr_t addr);
1325 : : phys_addr_t pci_pio_to_address(unsigned long pio);
1326 : : int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1327 : : int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1328 : : phys_addr_t phys_addr);
1329 : : void pci_unmap_iospace(struct resource *res);
1330 : : void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1331 : : resource_size_t offset,
1332 : : resource_size_t size);
1333 : : void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1334 : : struct resource *res);
1335 : :
1336 : 0 : static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1337 : : {
1338 : 0 : struct pci_bus_region region;
1339 : :
1340 : 0 : pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1341 [ # # ]: 0 : return region.start;
1342 : : }
1343 : :
1344 : : /* Proper probing supporting hot-pluggable devices */
1345 : : int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1346 : : const char *mod_name);
1347 : :
1348 : : /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1349 : : #define pci_register_driver(driver) \
1350 : : __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1351 : :
1352 : : void pci_unregister_driver(struct pci_driver *dev);
1353 : :
1354 : : /**
1355 : : * module_pci_driver() - Helper macro for registering a PCI driver
1356 : : * @__pci_driver: pci_driver struct
1357 : : *
1358 : : * Helper macro for PCI drivers which do not do anything special in module
1359 : : * init/exit. This eliminates a lot of boilerplate. Each module may only
1360 : : * use this macro once, and calling it replaces module_init() and module_exit()
1361 : : */
1362 : : #define module_pci_driver(__pci_driver) \
1363 : : module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1364 : :
1365 : : /**
1366 : : * builtin_pci_driver() - Helper macro for registering a PCI driver
1367 : : * @__pci_driver: pci_driver struct
1368 : : *
1369 : : * Helper macro for PCI drivers which do not do anything special in their
1370 : : * init code. This eliminates a lot of boilerplate. Each driver may only
1371 : : * use this macro once, and calling it replaces device_initcall(...)
1372 : : */
1373 : : #define builtin_pci_driver(__pci_driver) \
1374 : : builtin_driver(__pci_driver, pci_register_driver)
1375 : :
1376 : : struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1377 : : int pci_add_dynid(struct pci_driver *drv,
1378 : : unsigned int vendor, unsigned int device,
1379 : : unsigned int subvendor, unsigned int subdevice,
1380 : : unsigned int class, unsigned int class_mask,
1381 : : unsigned long driver_data);
1382 : : const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1383 : : struct pci_dev *dev);
1384 : : int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1385 : : int pass);
1386 : :
1387 : : void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1388 : : void *userdata);
1389 : : int pci_cfg_space_size(struct pci_dev *dev);
1390 : : unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1391 : : void pci_setup_bridge(struct pci_bus *bus);
1392 : : resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1393 : : unsigned long type);
1394 : :
1395 : : #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1396 : : #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1397 : :
1398 : : int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1399 : : unsigned int command_bits, u32 flags);
1400 : :
1401 : : /*
1402 : : * Virtual interrupts allow for more interrupts to be allocated
1403 : : * than the device has interrupts for. These are not programmed
1404 : : * into the device's MSI-X table and must be handled by some
1405 : : * other driver means.
1406 : : */
1407 : : #define PCI_IRQ_VIRTUAL (1 << 4)
1408 : :
1409 : : #define PCI_IRQ_ALL_TYPES \
1410 : : (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1411 : :
1412 : : /* kmem_cache style wrapper around pci_alloc_consistent() */
1413 : :
1414 : : #include <linux/dmapool.h>
1415 : :
1416 : : #define pci_pool dma_pool
1417 : : #define pci_pool_create(name, pdev, size, align, allocation) \
1418 : : dma_pool_create(name, &pdev->dev, size, align, allocation)
1419 : : #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1420 : : #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1421 : : #define pci_pool_zalloc(pool, flags, handle) \
1422 : : dma_pool_zalloc(pool, flags, handle)
1423 : : #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1424 : :
1425 : : struct msix_entry {
1426 : : u32 vector; /* Kernel uses to write allocated vector */
1427 : : u16 entry; /* Driver uses to specify entry, OS writes */
1428 : : };
1429 : :
1430 : : #ifdef CONFIG_PCI_MSI
1431 : : int pci_msi_vec_count(struct pci_dev *dev);
1432 : : void pci_disable_msi(struct pci_dev *dev);
1433 : : int pci_msix_vec_count(struct pci_dev *dev);
1434 : : void pci_disable_msix(struct pci_dev *dev);
1435 : : void pci_restore_msi_state(struct pci_dev *dev);
1436 : : int pci_msi_enabled(void);
1437 : : int pci_enable_msi(struct pci_dev *dev);
1438 : : int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1439 : : int minvec, int maxvec);
1440 : : static inline int pci_enable_msix_exact(struct pci_dev *dev,
1441 : : struct msix_entry *entries, int nvec)
1442 : : {
1443 : : int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1444 : : if (rc < 0)
1445 : : return rc;
1446 : : return 0;
1447 : : }
1448 : : int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1449 : : unsigned int max_vecs, unsigned int flags,
1450 : : struct irq_affinity *affd);
1451 : :
1452 : : void pci_free_irq_vectors(struct pci_dev *dev);
1453 : : int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1454 : : const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1455 : :
1456 : : #else
1457 : : static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1458 : : static inline void pci_disable_msi(struct pci_dev *dev) { }
1459 : : static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1460 : : static inline void pci_disable_msix(struct pci_dev *dev) { }
1461 : : static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1462 : : static inline int pci_msi_enabled(void) { return 0; }
1463 : : static inline int pci_enable_msi(struct pci_dev *dev)
1464 : : { return -ENOSYS; }
1465 : : static inline int pci_enable_msix_range(struct pci_dev *dev,
1466 : : struct msix_entry *entries, int minvec, int maxvec)
1467 : : { return -ENOSYS; }
1468 : : static inline int pci_enable_msix_exact(struct pci_dev *dev,
1469 : : struct msix_entry *entries, int nvec)
1470 : : { return -ENOSYS; }
1471 : :
1472 : : static inline int
1473 : : pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1474 : : unsigned int max_vecs, unsigned int flags,
1475 : : struct irq_affinity *aff_desc)
1476 : : {
1477 : : if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1478 : : return 1;
1479 : : return -ENOSPC;
1480 : : }
1481 : :
1482 : : static inline void pci_free_irq_vectors(struct pci_dev *dev)
1483 : : {
1484 : : }
1485 : :
1486 : : static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1487 : : {
1488 : : if (WARN_ON_ONCE(nr > 0))
1489 : : return -EINVAL;
1490 : : return dev->irq;
1491 : : }
1492 : : static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1493 : : int vec)
1494 : : {
1495 : : return cpu_possible_mask;
1496 : : }
1497 : : #endif
1498 : :
1499 : : /**
1500 : : * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1501 : : * @d: the INTx IRQ domain
1502 : : * @node: the DT node for the device whose interrupt we're translating
1503 : : * @intspec: the interrupt specifier data from the DT
1504 : : * @intsize: the number of entries in @intspec
1505 : : * @out_hwirq: pointer at which to write the hwirq number
1506 : : * @out_type: pointer at which to write the interrupt type
1507 : : *
1508 : : * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1509 : : * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1510 : : * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1511 : : * INTx value to obtain the hwirq number.
1512 : : *
1513 : : * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1514 : : */
1515 : : static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1516 : : struct device_node *node,
1517 : : const u32 *intspec,
1518 : : unsigned int intsize,
1519 : : unsigned long *out_hwirq,
1520 : : unsigned int *out_type)
1521 : : {
1522 : : const u32 intx = intspec[0];
1523 : :
1524 : : if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1525 : : return -EINVAL;
1526 : :
1527 : : *out_hwirq = intx - PCI_INTERRUPT_INTA;
1528 : : return 0;
1529 : : }
1530 : :
1531 : : #ifdef CONFIG_PCIEPORTBUS
1532 : : extern bool pcie_ports_disabled;
1533 : : extern bool pcie_ports_native;
1534 : : #else
1535 : : #define pcie_ports_disabled true
1536 : : #define pcie_ports_native false
1537 : : #endif
1538 : :
1539 : : #define PCIE_LINK_STATE_L0S BIT(0)
1540 : : #define PCIE_LINK_STATE_L1 BIT(1)
1541 : : #define PCIE_LINK_STATE_CLKPM BIT(2)
1542 : : #define PCIE_LINK_STATE_L1_1 BIT(3)
1543 : : #define PCIE_LINK_STATE_L1_2 BIT(4)
1544 : : #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1545 : : #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1546 : :
1547 : : #ifdef CONFIG_PCIEASPM
1548 : : int pci_disable_link_state(struct pci_dev *pdev, int state);
1549 : : int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1550 : : void pcie_no_aspm(void);
1551 : : bool pcie_aspm_support_enabled(void);
1552 : : bool pcie_aspm_enabled(struct pci_dev *pdev);
1553 : : #else
1554 : : static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1555 : : { return 0; }
1556 : : static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1557 : : { return 0; }
1558 : : static inline void pcie_no_aspm(void) { }
1559 : : static inline bool pcie_aspm_support_enabled(void) { return false; }
1560 : : static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1561 : : #endif
1562 : :
1563 : : #ifdef CONFIG_PCIEAER
1564 : : bool pci_aer_available(void);
1565 : : #else
1566 : : static inline bool pci_aer_available(void) { return false; }
1567 : : #endif
1568 : :
1569 : : bool pci_ats_disabled(void);
1570 : :
1571 : : void pci_cfg_access_lock(struct pci_dev *dev);
1572 : : bool pci_cfg_access_trylock(struct pci_dev *dev);
1573 : : void pci_cfg_access_unlock(struct pci_dev *dev);
1574 : :
1575 : : /*
1576 : : * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1577 : : * a PCI domain is defined to be a set of PCI buses which share
1578 : : * configuration space.
1579 : : */
1580 : : #ifdef CONFIG_PCI_DOMAINS
1581 : : extern int pci_domains_supported;
1582 : : #else
1583 : : enum { pci_domains_supported = 0 };
1584 : : static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1585 : : static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1586 : : #endif /* CONFIG_PCI_DOMAINS */
1587 : :
1588 : : /*
1589 : : * Generic implementation for PCI domain support. If your
1590 : : * architecture does not need custom management of PCI
1591 : : * domains then this implementation will be used
1592 : : */
1593 : : #ifdef CONFIG_PCI_DOMAINS_GENERIC
1594 : : static inline int pci_domain_nr(struct pci_bus *bus)
1595 : : {
1596 : : return bus->domain_nr;
1597 : : }
1598 : : #ifdef CONFIG_ACPI
1599 : : int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1600 : : #else
1601 : : static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1602 : : { return 0; }
1603 : : #endif
1604 : : int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1605 : : #endif
1606 : :
1607 : : /* Some architectures require additional setup to direct VGA traffic */
1608 : : typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1609 : : unsigned int command_bits, u32 flags);
1610 : : void pci_register_set_vga_state(arch_set_vga_state_t func);
1611 : :
1612 : : static inline int
1613 : : pci_request_io_regions(struct pci_dev *pdev, const char *name)
1614 : : {
1615 : : return pci_request_selected_regions(pdev,
1616 : : pci_select_bars(pdev, IORESOURCE_IO), name);
1617 : : }
1618 : :
1619 : : static inline void
1620 : : pci_release_io_regions(struct pci_dev *pdev)
1621 : : {
1622 : : return pci_release_selected_regions(pdev,
1623 : : pci_select_bars(pdev, IORESOURCE_IO));
1624 : : }
1625 : :
1626 : : static inline int
1627 : : pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1628 : : {
1629 : : return pci_request_selected_regions(pdev,
1630 : : pci_select_bars(pdev, IORESOURCE_MEM), name);
1631 : : }
1632 : :
1633 : : static inline void
1634 : : pci_release_mem_regions(struct pci_dev *pdev)
1635 : : {
1636 : : return pci_release_selected_regions(pdev,
1637 : : pci_select_bars(pdev, IORESOURCE_MEM));
1638 : : }
1639 : :
1640 : : #else /* CONFIG_PCI is not enabled */
1641 : :
1642 : : static inline void pci_set_flags(int flags) { }
1643 : : static inline void pci_add_flags(int flags) { }
1644 : : static inline void pci_clear_flags(int flags) { }
1645 : : static inline int pci_has_flag(int flag) { return 0; }
1646 : :
1647 : : /*
1648 : : * If the system does not have PCI, clearly these return errors. Define
1649 : : * these as simple inline functions to avoid hair in drivers.
1650 : : */
1651 : : #define _PCI_NOP(o, s, t) \
1652 : : static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1653 : : int where, t val) \
1654 : : { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1655 : :
1656 : : #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1657 : : _PCI_NOP(o, word, u16 x) \
1658 : : _PCI_NOP(o, dword, u32 x)
1659 : : _PCI_NOP_ALL(read, *)
1660 : : _PCI_NOP_ALL(write,)
1661 : :
1662 : : static inline struct pci_dev *pci_get_device(unsigned int vendor,
1663 : : unsigned int device,
1664 : : struct pci_dev *from)
1665 : : { return NULL; }
1666 : :
1667 : : static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1668 : : unsigned int device,
1669 : : unsigned int ss_vendor,
1670 : : unsigned int ss_device,
1671 : : struct pci_dev *from)
1672 : : { return NULL; }
1673 : :
1674 : : static inline struct pci_dev *pci_get_class(unsigned int class,
1675 : : struct pci_dev *from)
1676 : : { return NULL; }
1677 : :
1678 : : #define pci_dev_present(ids) (0)
1679 : : #define no_pci_devices() (1)
1680 : : #define pci_dev_put(dev) do { } while (0)
1681 : :
1682 : : static inline void pci_set_master(struct pci_dev *dev) { }
1683 : : static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1684 : : static inline void pci_disable_device(struct pci_dev *dev) { }
1685 : : static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1686 : : static inline int pci_assign_resource(struct pci_dev *dev, int i)
1687 : : { return -EBUSY; }
1688 : : static inline int __pci_register_driver(struct pci_driver *drv,
1689 : : struct module *owner)
1690 : : { return 0; }
1691 : : static inline int pci_register_driver(struct pci_driver *drv)
1692 : : { return 0; }
1693 : : static inline void pci_unregister_driver(struct pci_driver *drv) { }
1694 : : static inline int pci_find_capability(struct pci_dev *dev, int cap)
1695 : : { return 0; }
1696 : : static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1697 : : int cap)
1698 : : { return 0; }
1699 : : static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1700 : : { return 0; }
1701 : :
1702 : : /* Power management related routines */
1703 : : static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1704 : : static inline void pci_restore_state(struct pci_dev *dev) { }
1705 : : static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1706 : : { return 0; }
1707 : : static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1708 : : { return 0; }
1709 : : static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1710 : : pm_message_t state)
1711 : : { return PCI_D0; }
1712 : : static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1713 : : int enable)
1714 : : { return 0; }
1715 : :
1716 : : static inline struct resource *pci_find_resource(struct pci_dev *dev,
1717 : : struct resource *res)
1718 : : { return NULL; }
1719 : : static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1720 : : { return -EIO; }
1721 : : static inline void pci_release_regions(struct pci_dev *dev) { }
1722 : :
1723 : : static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1724 : :
1725 : : static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1726 : : { return NULL; }
1727 : : static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1728 : : unsigned int devfn)
1729 : : { return NULL; }
1730 : : static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1731 : : unsigned int bus, unsigned int devfn)
1732 : : { return NULL; }
1733 : :
1734 : : static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1735 : : static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1736 : :
1737 : : #define dev_is_pci(d) (false)
1738 : : #define dev_is_pf(d) (false)
1739 : : static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1740 : : { return false; }
1741 : : static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1742 : : struct device_node *node,
1743 : : const u32 *intspec,
1744 : : unsigned int intsize,
1745 : : unsigned long *out_hwirq,
1746 : : unsigned int *out_type)
1747 : : { return -EINVAL; }
1748 : :
1749 : : static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1750 : : struct pci_dev *dev)
1751 : : { return NULL; }
1752 : : static inline bool pci_ats_disabled(void) { return true; }
1753 : :
1754 : : static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1755 : : {
1756 : : return -EINVAL;
1757 : : }
1758 : :
1759 : : static inline int
1760 : : pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1761 : : unsigned int max_vecs, unsigned int flags,
1762 : : struct irq_affinity *aff_desc)
1763 : : {
1764 : : return -ENOSPC;
1765 : : }
1766 : : #endif /* CONFIG_PCI */
1767 : :
1768 : : static inline int
1769 : 0 : pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1770 : : unsigned int max_vecs, unsigned int flags)
1771 : : {
1772 : 0 : return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1773 : : NULL);
1774 : : }
1775 : :
1776 : : /* Include architecture-dependent settings and functions */
1777 : :
1778 : : #include <asm/pci.h>
1779 : :
1780 : : /* These two functions provide almost identical functionality. Depending
1781 : : * on the architecture, one will be implemented as a wrapper around the
1782 : : * other (in drivers/pci/mmap.c).
1783 : : *
1784 : : * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1785 : : * is expected to be an offset within that region.
1786 : : *
1787 : : * pci_mmap_page_range() is the legacy architecture-specific interface,
1788 : : * which accepts a "user visible" resource address converted by
1789 : : * pci_resource_to_user(), as used in the legacy mmap() interface in
1790 : : * /proc/bus/pci/.
1791 : : */
1792 : : int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1793 : : struct vm_area_struct *vma,
1794 : : enum pci_mmap_state mmap_state, int write_combine);
1795 : : int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1796 : : struct vm_area_struct *vma,
1797 : : enum pci_mmap_state mmap_state, int write_combine);
1798 : :
1799 : : #ifndef arch_can_pci_mmap_wc
1800 : : #define arch_can_pci_mmap_wc() 0
1801 : : #endif
1802 : :
1803 : : #ifndef arch_can_pci_mmap_io
1804 : : #define arch_can_pci_mmap_io() 0
1805 : : #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1806 : : #else
1807 : : int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1808 : : #endif
1809 : :
1810 : : #ifndef pci_root_bus_fwnode
1811 : : #define pci_root_bus_fwnode(bus) NULL
1812 : : #endif
1813 : :
1814 : : /*
1815 : : * These helpers provide future and backwards compatibility
1816 : : * for accessing popular PCI BAR info
1817 : : */
1818 : : #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1819 : : #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1820 : : #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1821 : : #define pci_resource_len(dev,bar) \
1822 : : ((pci_resource_start((dev), (bar)) == 0 && \
1823 : : pci_resource_end((dev), (bar)) == \
1824 : : pci_resource_start((dev), (bar))) ? 0 : \
1825 : : \
1826 : : (pci_resource_end((dev), (bar)) - \
1827 : : pci_resource_start((dev), (bar)) + 1))
1828 : :
1829 : : /*
1830 : : * Similar to the helpers above, these manipulate per-pci_dev
1831 : : * driver-specific data. They are really just a wrapper around
1832 : : * the generic device structure functions of these calls.
1833 : : */
1834 : 0 : static inline void *pci_get_drvdata(struct pci_dev *pdev)
1835 : : {
1836 [ # # # # : 0 : return dev_get_drvdata(&pdev->dev);
# # # # ]
1837 : : }
1838 : :
1839 : 21 : static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1840 : : {
1841 [ # # ]: 21 : dev_set_drvdata(&pdev->dev, data);
1842 : 0 : }
1843 : :
1844 : 2736 : static inline const char *pci_name(const struct pci_dev *pdev)
1845 : : {
1846 [ + - + - : 2736 : return dev_name(&pdev->dev);
+ - - - -
- - - # #
# # # # #
# # # # #
# # ]
1847 : : }
1848 : :
1849 : : void pci_resource_to_user(const struct pci_dev *dev, int bar,
1850 : : const struct resource *rsrc,
1851 : : resource_size_t *start, resource_size_t *end);
1852 : :
1853 : : /*
1854 : : * The world is not perfect and supplies us with broken PCI devices.
1855 : : * For at least a part of these bugs we need a work-around, so both
1856 : : * generic (drivers/pci/quirks.c) and per-architecture code can define
1857 : : * fixup hooks to be called for particular buggy devices.
1858 : : */
1859 : :
1860 : : struct pci_fixup {
1861 : : u16 vendor; /* Or PCI_ANY_ID */
1862 : : u16 device; /* Or PCI_ANY_ID */
1863 : : u32 class; /* Or PCI_ANY_ID */
1864 : : unsigned int class_shift; /* should be 0, 8, 16 */
1865 : : #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1866 : : int hook_offset;
1867 : : #else
1868 : : void (*hook)(struct pci_dev *dev);
1869 : : #endif
1870 : : };
1871 : :
1872 : : enum pci_fixup_pass {
1873 : : pci_fixup_early, /* Before probing BARs */
1874 : : pci_fixup_header, /* After reading configuration header */
1875 : : pci_fixup_final, /* Final phase of device fixups */
1876 : : pci_fixup_enable, /* pci_enable_device() time */
1877 : : pci_fixup_resume, /* pci_device_resume() */
1878 : : pci_fixup_suspend, /* pci_device_suspend() */
1879 : : pci_fixup_resume_early, /* pci_device_resume_early() */
1880 : : pci_fixup_suspend_late, /* pci_device_suspend_late() */
1881 : : };
1882 : :
1883 : : #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1884 : : #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1885 : : class_shift, hook) \
1886 : : __ADDRESSABLE(hook) \
1887 : : asm(".section " #sec ", \"a\" \n" \
1888 : : ".balign 16 \n" \
1889 : : ".short " #vendor ", " #device " \n" \
1890 : : ".long " #class ", " #class_shift " \n" \
1891 : : ".long " #hook " - . \n" \
1892 : : ".previous \n");
1893 : : #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1894 : : class_shift, hook) \
1895 : : __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1896 : : class_shift, hook)
1897 : : #else
1898 : : /* Anonymous variables would be nice... */
1899 : : #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1900 : : class_shift, hook) \
1901 : : static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1902 : : __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1903 : : = { vendor, device, class, class_shift, hook };
1904 : : #endif
1905 : :
1906 : : #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1907 : : class_shift, hook) \
1908 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1909 : : hook, vendor, device, class, class_shift, hook)
1910 : : #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1911 : : class_shift, hook) \
1912 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1913 : : hook, vendor, device, class, class_shift, hook)
1914 : : #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1915 : : class_shift, hook) \
1916 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1917 : : hook, vendor, device, class, class_shift, hook)
1918 : : #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1919 : : class_shift, hook) \
1920 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1921 : : hook, vendor, device, class, class_shift, hook)
1922 : : #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1923 : : class_shift, hook) \
1924 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1925 : : resume##hook, vendor, device, class, class_shift, hook)
1926 : : #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1927 : : class_shift, hook) \
1928 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1929 : : resume_early##hook, vendor, device, class, class_shift, hook)
1930 : : #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1931 : : class_shift, hook) \
1932 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1933 : : suspend##hook, vendor, device, class, class_shift, hook)
1934 : : #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1935 : : class_shift, hook) \
1936 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1937 : : suspend_late##hook, vendor, device, class, class_shift, hook)
1938 : :
1939 : : #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1940 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1941 : : hook, vendor, device, PCI_ANY_ID, 0, hook)
1942 : : #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1943 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1944 : : hook, vendor, device, PCI_ANY_ID, 0, hook)
1945 : : #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1946 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1947 : : hook, vendor, device, PCI_ANY_ID, 0, hook)
1948 : : #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1949 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1950 : : hook, vendor, device, PCI_ANY_ID, 0, hook)
1951 : : #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1952 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1953 : : resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1954 : : #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1955 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1956 : : resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1957 : : #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1958 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1959 : : suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1960 : : #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1961 : : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1962 : : suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1963 : :
1964 : : #ifdef CONFIG_PCI_QUIRKS
1965 : : void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1966 : : #else
1967 : : static inline void pci_fixup_device(enum pci_fixup_pass pass,
1968 : : struct pci_dev *dev) { }
1969 : : #endif
1970 : :
1971 : : void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1972 : : void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1973 : : void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1974 : : int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1975 : : int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1976 : : const char *name);
1977 : : void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1978 : :
1979 : : extern int pci_pci_problems;
1980 : : #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1981 : : #define PCIPCI_TRITON 2
1982 : : #define PCIPCI_NATOMA 4
1983 : : #define PCIPCI_VIAETBF 8
1984 : : #define PCIPCI_VSFX 16
1985 : : #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1986 : : #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1987 : :
1988 : : extern unsigned long pci_cardbus_io_size;
1989 : : extern unsigned long pci_cardbus_mem_size;
1990 : : extern u8 pci_dfl_cache_line_size;
1991 : : extern u8 pci_cache_line_size;
1992 : :
1993 : : /* Architecture-specific versions may override these (weak) */
1994 : : void pcibios_disable_device(struct pci_dev *dev);
1995 : : void pcibios_set_master(struct pci_dev *dev);
1996 : : int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1997 : : enum pcie_reset_state state);
1998 : : int pcibios_add_device(struct pci_dev *dev);
1999 : : void pcibios_release_device(struct pci_dev *dev);
2000 : : #ifdef CONFIG_PCI
2001 : : void pcibios_penalize_isa_irq(int irq, int active);
2002 : : #else
2003 : : static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2004 : : #endif
2005 : : int pcibios_alloc_irq(struct pci_dev *dev);
2006 : : void pcibios_free_irq(struct pci_dev *dev);
2007 : : resource_size_t pcibios_default_alignment(void);
2008 : :
2009 : : #ifdef CONFIG_HIBERNATE_CALLBACKS
2010 : : extern struct dev_pm_ops pcibios_pm_ops;
2011 : : #endif
2012 : :
2013 : : #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2014 : : void __init pci_mmcfg_early_init(void);
2015 : : void __init pci_mmcfg_late_init(void);
2016 : : #else
2017 : : static inline void pci_mmcfg_early_init(void) { }
2018 : : static inline void pci_mmcfg_late_init(void) { }
2019 : : #endif
2020 : :
2021 : : int pci_ext_cfg_avail(void);
2022 : :
2023 : : void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2024 : : void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2025 : :
2026 : : #ifdef CONFIG_PCI_IOV
2027 : : int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2028 : : int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2029 : :
2030 : : int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2031 : : void pci_disable_sriov(struct pci_dev *dev);
2032 : : int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2033 : : void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2034 : : int pci_num_vf(struct pci_dev *dev);
2035 : : int pci_vfs_assigned(struct pci_dev *dev);
2036 : : int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2037 : : int pci_sriov_get_totalvfs(struct pci_dev *dev);
2038 : : int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2039 : : resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2040 : : void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2041 : :
2042 : : /* Arch may override these (weak) */
2043 : : int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2044 : : int pcibios_sriov_disable(struct pci_dev *pdev);
2045 : : resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2046 : : #else
2047 : : static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2048 : : {
2049 : : return -ENOSYS;
2050 : : }
2051 : : static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2052 : : {
2053 : : return -ENOSYS;
2054 : : }
2055 : 0 : static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2056 : 0 : { return -ENODEV; }
2057 : : static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2058 : : {
2059 : : return -ENOSYS;
2060 : : }
2061 : : static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2062 : : int id) { }
2063 : 0 : static inline void pci_disable_sriov(struct pci_dev *dev) { }
2064 : 63 : static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2065 : 0 : static inline int pci_vfs_assigned(struct pci_dev *dev)
2066 [ # # ]: 0 : { return 0; }
2067 : : static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2068 : : { return 0; }
2069 : : static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2070 : : { return 0; }
2071 : : #define pci_sriov_configure_simple NULL
2072 : : static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2073 : : { return 0; }
2074 : : static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2075 : : #endif
2076 : :
2077 : : #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2078 : : void pci_hp_create_module_link(struct pci_slot *pci_slot);
2079 : : void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2080 : : #endif
2081 : :
2082 : : /**
2083 : : * pci_pcie_cap - get the saved PCIe capability offset
2084 : : * @dev: PCI device
2085 : : *
2086 : : * PCIe capability offset is calculated at PCI device initialization
2087 : : * time and saved in the data structure. This function returns saved
2088 : : * PCIe capability offset. Using this instead of pci_find_capability()
2089 : : * reduces unnecessary search in the PCI configuration space. If you
2090 : : * need to calculate PCIe capability offset from raw device for some
2091 : : * reasons, please use pci_find_capability() instead.
2092 : : */
2093 : 3318 : static inline int pci_pcie_cap(struct pci_dev *dev)
2094 : : {
2095 [ # # # # : 2478 : return dev->pcie_cap;
# # # # ]
2096 : : }
2097 : :
2098 : : /**
2099 : : * pci_is_pcie - check if the PCI device is PCI Express capable
2100 : : * @dev: PCI device
2101 : : *
2102 : : * Returns: true if the PCI device is PCI Express capable, false otherwise.
2103 : : */
2104 : 3318 : static inline bool pci_is_pcie(struct pci_dev *dev)
2105 : : {
2106 [ - + - + : 3318 : return pci_pcie_cap(dev);
- + + - -
+ - + - +
- + - + -
+ - + - -
- - - - -
- ]
2107 : : }
2108 : :
2109 : : /**
2110 : : * pcie_caps_reg - get the PCIe Capabilities Register
2111 : : * @dev: PCI device
2112 : : */
2113 : 126 : static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2114 : : {
2115 [ # # ]: 126 : return dev->pcie_flags_reg;
2116 : : }
2117 : :
2118 : : /**
2119 : : * pci_pcie_type - get the PCIe device/port type
2120 : : * @dev: PCI device
2121 : : */
2122 : 126 : static inline int pci_pcie_type(const struct pci_dev *dev)
2123 : : {
2124 [ - + - - : 126 : return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
2125 : : }
2126 : :
2127 : 0 : static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2128 : : {
2129 : 0 : while (1) {
2130 [ # # ]: 0 : if (!pci_is_pcie(dev))
2131 : : break;
2132 [ # # ]: 0 : if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2133 : : return dev;
2134 [ # # ]: 0 : if (!dev->bus->self)
2135 : : break;
2136 : : dev = dev->bus->self;
2137 : : }
2138 : : return NULL;
2139 : : }
2140 : :
2141 : : void pci_request_acs(void);
2142 : : bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2143 : : bool pci_acs_path_enabled(struct pci_dev *start,
2144 : : struct pci_dev *end, u16 acs_flags);
2145 : : int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2146 : :
2147 : : #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2148 : : #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2149 : :
2150 : : /* Large Resource Data Type Tag Item Names */
2151 : : #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2152 : : #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2153 : : #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2154 : :
2155 : : #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2156 : : #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2157 : : #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2158 : :
2159 : : /* Small Resource Data Type Tag Item Names */
2160 : : #define PCI_VPD_STIN_END 0x0f /* End */
2161 : :
2162 : : #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2163 : :
2164 : : #define PCI_VPD_SRDT_TIN_MASK 0x78
2165 : : #define PCI_VPD_SRDT_LEN_MASK 0x07
2166 : : #define PCI_VPD_LRDT_TIN_MASK 0x7f
2167 : :
2168 : : #define PCI_VPD_LRDT_TAG_SIZE 3
2169 : : #define PCI_VPD_SRDT_TAG_SIZE 1
2170 : :
2171 : : #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2172 : :
2173 : : #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2174 : : #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2175 : : #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2176 : : #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2177 : :
2178 : : /**
2179 : : * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2180 : : * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2181 : : *
2182 : : * Returns the extracted Large Resource Data Type length.
2183 : : */
2184 : 0 : static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2185 : : {
2186 [ # # # # ]: 0 : return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2187 : : }
2188 : :
2189 : : /**
2190 : : * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2191 : : * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2192 : : *
2193 : : * Returns the extracted Large Resource Data Type Tag item.
2194 : : */
2195 : 0 : static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2196 : : {
2197 [ # # ]: 0 : return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2198 : : }
2199 : :
2200 : : /**
2201 : : * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2202 : : * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2203 : : *
2204 : : * Returns the extracted Small Resource Data Type length.
2205 : : */
2206 : 0 : static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2207 : : {
2208 : 0 : return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2209 : : }
2210 : :
2211 : : /**
2212 : : * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2213 : : * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2214 : : *
2215 : : * Returns the extracted Small Resource Data Type Tag Item.
2216 : : */
2217 : 0 : static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2218 : : {
2219 : 0 : return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2220 : : }
2221 : :
2222 : : /**
2223 : : * pci_vpd_info_field_size - Extracts the information field length
2224 : : * @info_field: Pointer to the beginning of an information field header
2225 : : *
2226 : : * Returns the extracted information field length.
2227 : : */
2228 : 0 : static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2229 : : {
2230 [ # # # # : 0 : return info_field[2];
# # ]
2231 : : }
2232 : :
2233 : : /**
2234 : : * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2235 : : * @buf: Pointer to buffered vpd data
2236 : : * @off: The offset into the buffer at which to begin the search
2237 : : * @len: The length of the vpd buffer
2238 : : * @rdt: The Resource Data Type to search for
2239 : : *
2240 : : * Returns the index where the Resource Data Type was found or
2241 : : * -ENOENT otherwise.
2242 : : */
2243 : : int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2244 : :
2245 : : /**
2246 : : * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2247 : : * @buf: Pointer to buffered vpd data
2248 : : * @off: The offset into the buffer at which to begin the search
2249 : : * @len: The length of the buffer area, relative to off, in which to search
2250 : : * @kw: The keyword to search for
2251 : : *
2252 : : * Returns the index where the information field keyword was found or
2253 : : * -ENOENT otherwise.
2254 : : */
2255 : : int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2256 : : unsigned int len, const char *kw);
2257 : :
2258 : : /* PCI <-> OF binding helpers */
2259 : : #ifdef CONFIG_OF
2260 : : struct device_node;
2261 : : struct irq_domain;
2262 : : struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2263 : : int pci_parse_request_of_pci_ranges(struct device *dev,
2264 : : struct list_head *resources,
2265 : : struct list_head *ib_resources,
2266 : : struct resource **bus_range);
2267 : :
2268 : : /* Arch may override this (weak) */
2269 : : struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2270 : :
2271 : : #else /* CONFIG_OF */
2272 : : static inline struct irq_domain *
2273 : 21 : pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2274 : : static inline int
2275 : : pci_parse_request_of_pci_ranges(struct device *dev,
2276 : : struct list_head *resources,
2277 : : struct list_head *ib_resources,
2278 : : struct resource **bus_range)
2279 : : {
2280 : : return -EINVAL;
2281 : : }
2282 : : #endif /* CONFIG_OF */
2283 : :
2284 : : static inline struct device_node *
2285 : : pci_device_to_OF_node(const struct pci_dev *pdev)
2286 : : {
2287 : : return pdev ? pdev->dev.of_node : NULL;
2288 : : }
2289 : :
2290 : : static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2291 : : {
2292 : : return bus ? bus->dev.of_node : NULL;
2293 : : }
2294 : :
2295 : : #ifdef CONFIG_ACPI
2296 : : struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2297 : :
2298 : : void
2299 : : pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2300 : : bool pci_pr3_present(struct pci_dev *pdev);
2301 : : #else
2302 : : static inline struct irq_domain *
2303 : : pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2304 : : static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2305 : : #endif
2306 : :
2307 : : #ifdef CONFIG_EEH
2308 : : static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2309 : : {
2310 : : return pdev->dev.archdata.edev;
2311 : : }
2312 : : #endif
2313 : :
2314 : : void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2315 : : bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2316 : : int pci_for_each_dma_alias(struct pci_dev *pdev,
2317 : : int (*fn)(struct pci_dev *pdev,
2318 : : u16 alias, void *data), void *data);
2319 : :
2320 : : /* Helper functions for operation of device flag */
2321 : : static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2322 : : {
2323 : : pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2324 : : }
2325 : : static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2326 : : {
2327 : : pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2328 : : }
2329 : : static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2330 : : {
2331 : : return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2332 : : }
2333 : :
2334 : : /**
2335 : : * pci_ari_enabled - query ARI forwarding status
2336 : : * @bus: the PCI bus
2337 : : *
2338 : : * Returns true if ARI forwarding is enabled.
2339 : : */
2340 : 273 : static inline bool pci_ari_enabled(struct pci_bus *bus)
2341 : : {
2342 [ - + - - : 525 : return bus->self && bus->self->ari_enabled;
- + # # #
# # # # #
# # # # ]
2343 : : }
2344 : :
2345 : : /**
2346 : : * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2347 : : * @pdev: PCI device to check
2348 : : *
2349 : : * Walk upwards from @pdev and check for each encountered bridge if it's part
2350 : : * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2351 : : * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2352 : : */
2353 : : static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2354 : : {
2355 : : struct pci_dev *parent = pdev;
2356 : :
2357 : : if (pdev->is_thunderbolt)
2358 : : return true;
2359 : :
2360 : : while ((parent = pci_upstream_bridge(parent)))
2361 : : if (parent->is_thunderbolt)
2362 : : return true;
2363 : :
2364 : : return false;
2365 : : }
2366 : :
2367 : : #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2368 : : void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2369 : : #endif
2370 : :
2371 : : /* Provide the legacy pci_dma_* API */
2372 : : #include <linux/pci-dma-compat.h>
2373 : :
2374 : : #define pci_printk(level, pdev, fmt, arg...) \
2375 : : dev_printk(level, &(pdev)->dev, fmt, ##arg)
2376 : :
2377 : : #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2378 : : #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2379 : : #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2380 : : #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2381 : : #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2382 : : #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2383 : : #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2384 : : #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2385 : :
2386 : : #define pci_notice_ratelimited(pdev, fmt, arg...) \
2387 : : dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2388 : :
2389 : : #define pci_info_ratelimited(pdev, fmt, arg...) \
2390 : : dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2391 : :
2392 : : #define pci_WARN(pdev, condition, fmt, arg...) \
2393 : : WARN(condition, "%s %s: " fmt, \
2394 : : dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2395 : :
2396 : : #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2397 : : WARN_ONCE(condition, "%s %s: " fmt, \
2398 : : dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2399 : :
2400 : : #endif /* LINUX_PCI_H */
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