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1 : : /* SPDX-License-Identifier: GPL-2.0 */
2 : : #ifndef __LINUX_GPIO_DRIVER_H
3 : : #define __LINUX_GPIO_DRIVER_H
4 : :
5 : : #include <linux/device.h>
6 : : #include <linux/types.h>
7 : : #include <linux/irq.h>
8 : : #include <linux/irqchip/chained_irq.h>
9 : : #include <linux/irqdomain.h>
10 : : #include <linux/lockdep.h>
11 : : #include <linux/pinctrl/pinctrl.h>
12 : : #include <linux/pinctrl/pinconf-generic.h>
13 : :
14 : : struct gpio_desc;
15 : : struct of_phandle_args;
16 : : struct device_node;
17 : : struct seq_file;
18 : : struct gpio_device;
19 : : struct module;
20 : : enum gpiod_flags;
21 : : enum gpio_lookup_flags;
22 : :
23 : : struct gpio_chip;
24 : :
25 : : /**
26 : : * struct gpio_irq_chip - GPIO interrupt controller
27 : : */
28 : : struct gpio_irq_chip {
29 : : /**
30 : : * @chip:
31 : : *
32 : : * GPIO IRQ chip implementation, provided by GPIO driver.
33 : : */
34 : : struct irq_chip *chip;
35 : :
36 : : /**
37 : : * @domain:
38 : : *
39 : : * Interrupt translation domain; responsible for mapping between GPIO
40 : : * hwirq number and Linux IRQ number.
41 : : */
42 : : struct irq_domain *domain;
43 : :
44 : : /**
45 : : * @domain_ops:
46 : : *
47 : : * Table of interrupt domain operations for this IRQ chip.
48 : : */
49 : : const struct irq_domain_ops *domain_ops;
50 : :
51 : : #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
52 : : /**
53 : : * @fwnode:
54 : : *
55 : : * Firmware node corresponding to this gpiochip/irqchip, necessary
56 : : * for hierarchical irqdomain support.
57 : : */
58 : : struct fwnode_handle *fwnode;
59 : :
60 : : /**
61 : : * @parent_domain:
62 : : *
63 : : * If non-NULL, will be set as the parent of this GPIO interrupt
64 : : * controller's IRQ domain to establish a hierarchical interrupt
65 : : * domain. The presence of this will activate the hierarchical
66 : : * interrupt support.
67 : : */
68 : : struct irq_domain *parent_domain;
69 : :
70 : : /**
71 : : * @child_to_parent_hwirq:
72 : : *
73 : : * This callback translates a child hardware IRQ offset to a parent
74 : : * hardware IRQ offset on a hierarchical interrupt chip. The child
75 : : * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
76 : : * ngpio field of struct gpio_chip) and the corresponding parent
77 : : * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
78 : : * the driver. The driver can calculate this from an offset or using
79 : : * a lookup table or whatever method is best for this chip. Return
80 : : * 0 on successful translation in the driver.
81 : : *
82 : : * If some ranges of hardware IRQs do not have a corresponding parent
83 : : * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
84 : : * @need_valid_mask to make these GPIO lines unavailable for
85 : : * translation.
86 : : */
87 : : int (*child_to_parent_hwirq)(struct gpio_chip *chip,
88 : : unsigned int child_hwirq,
89 : : unsigned int child_type,
90 : : unsigned int *parent_hwirq,
91 : : unsigned int *parent_type);
92 : :
93 : : /**
94 : : * @populate_parent_fwspec:
95 : : *
96 : : * This optional callback populates the &struct irq_fwspec for the
97 : : * parent's IRQ domain. If this is not specified, then
98 : : * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
99 : : * variant named &gpiochip_populate_parent_fwspec_fourcell is also
100 : : * available.
101 : : */
102 : : void (*populate_parent_fwspec)(struct gpio_chip *chip,
103 : : struct irq_fwspec *fwspec,
104 : : unsigned int parent_hwirq,
105 : : unsigned int parent_type);
106 : :
107 : : /**
108 : : * @child_offset_to_irq:
109 : : *
110 : : * This optional callback is used to translate the child's GPIO line
111 : : * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
112 : : * callback. If this is not specified, then a default callback will be
113 : : * provided that returns the line offset.
114 : : */
115 : : unsigned int (*child_offset_to_irq)(struct gpio_chip *chip,
116 : : unsigned int pin);
117 : :
118 : : /**
119 : : * @child_irq_domain_ops:
120 : : *
121 : : * The IRQ domain operations that will be used for this GPIO IRQ
122 : : * chip. If no operations are provided, then default callbacks will
123 : : * be populated to setup the IRQ hierarchy. Some drivers need to
124 : : * supply their own translate function.
125 : : */
126 : : struct irq_domain_ops child_irq_domain_ops;
127 : : #endif
128 : :
129 : : /**
130 : : * @handler:
131 : : *
132 : : * The IRQ handler to use (often a predefined IRQ core function) for
133 : : * GPIO IRQs, provided by GPIO driver.
134 : : */
135 : : irq_flow_handler_t handler;
136 : :
137 : : /**
138 : : * @default_type:
139 : : *
140 : : * Default IRQ triggering type applied during GPIO driver
141 : : * initialization, provided by GPIO driver.
142 : : */
143 : : unsigned int default_type;
144 : :
145 : : /**
146 : : * @lock_key:
147 : : *
148 : : * Per GPIO IRQ chip lockdep class for IRQ lock.
149 : : */
150 : : struct lock_class_key *lock_key;
151 : :
152 : : /**
153 : : * @request_key:
154 : : *
155 : : * Per GPIO IRQ chip lockdep class for IRQ request.
156 : : */
157 : : struct lock_class_key *request_key;
158 : :
159 : : /**
160 : : * @parent_handler:
161 : : *
162 : : * The interrupt handler for the GPIO chip's parent interrupts, may be
163 : : * NULL if the parent interrupts are nested rather than cascaded.
164 : : */
165 : : irq_flow_handler_t parent_handler;
166 : :
167 : : /**
168 : : * @parent_handler_data:
169 : : *
170 : : * Data associated, and passed to, the handler for the parent
171 : : * interrupt.
172 : : */
173 : : void *parent_handler_data;
174 : :
175 : : /**
176 : : * @num_parents:
177 : : *
178 : : * The number of interrupt parents of a GPIO chip.
179 : : */
180 : : unsigned int num_parents;
181 : :
182 : : /**
183 : : * @parents:
184 : : *
185 : : * A list of interrupt parents of a GPIO chip. This is owned by the
186 : : * driver, so the core will only reference this list, not modify it.
187 : : */
188 : : unsigned int *parents;
189 : :
190 : : /**
191 : : * @map:
192 : : *
193 : : * A list of interrupt parents for each line of a GPIO chip.
194 : : */
195 : : unsigned int *map;
196 : :
197 : : /**
198 : : * @threaded:
199 : : *
200 : : * True if set the interrupt handling uses nested threads.
201 : : */
202 : : bool threaded;
203 : :
204 : : /**
205 : : * @init_hw: optional routine to initialize hardware before
206 : : * an IRQ chip will be added. This is quite useful when
207 : : * a particular driver wants to clear IRQ related registers
208 : : * in order to avoid undesired events.
209 : : */
210 : : int (*init_hw)(struct gpio_chip *chip);
211 : :
212 : : /**
213 : : * @init_valid_mask: optional routine to initialize @valid_mask, to be
214 : : * used if not all GPIO lines are valid interrupts. Sometimes some
215 : : * lines just cannot fire interrupts, and this routine, when defined,
216 : : * is passed a bitmap in "valid_mask" and it will have ngpios
217 : : * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
218 : : * then directly set some bits to "0" if they cannot be used for
219 : : * interrupts.
220 : : */
221 : : void (*init_valid_mask)(struct gpio_chip *chip,
222 : : unsigned long *valid_mask,
223 : : unsigned int ngpios);
224 : :
225 : : /**
226 : : * @valid_mask:
227 : : *
228 : : * If not %NULL holds bitmask of GPIOs which are valid to be included
229 : : * in IRQ domain of the chip.
230 : : */
231 : : unsigned long *valid_mask;
232 : :
233 : : /**
234 : : * @first:
235 : : *
236 : : * Required for static IRQ allocation. If set, irq_domain_add_simple()
237 : : * will allocate and map all IRQs during initialization.
238 : : */
239 : : unsigned int first;
240 : :
241 : : /**
242 : : * @irq_enable:
243 : : *
244 : : * Store old irq_chip irq_enable callback
245 : : */
246 : : void (*irq_enable)(struct irq_data *data);
247 : :
248 : : /**
249 : : * @irq_disable:
250 : : *
251 : : * Store old irq_chip irq_disable callback
252 : : */
253 : : void (*irq_disable)(struct irq_data *data);
254 : : };
255 : :
256 : : /**
257 : : * struct gpio_chip - abstract a GPIO controller
258 : : * @label: a functional name for the GPIO device, such as a part
259 : : * number or the name of the SoC IP-block implementing it.
260 : : * @gpiodev: the internal state holder, opaque struct
261 : : * @parent: optional parent device providing the GPIOs
262 : : * @owner: helps prevent removal of modules exporting active GPIOs
263 : : * @request: optional hook for chip-specific activation, such as
264 : : * enabling module power and clock; may sleep
265 : : * @free: optional hook for chip-specific deactivation, such as
266 : : * disabling module power and clock; may sleep
267 : : * @get_direction: returns direction for signal "offset", 0=out, 1=in,
268 : : * (same as GPIOF_DIR_XXX), or negative error.
269 : : * It is recommended to always implement this function, even on
270 : : * input-only or output-only gpio chips.
271 : : * @direction_input: configures signal "offset" as input, or returns error
272 : : * This can be omitted on input-only or output-only gpio chips.
273 : : * @direction_output: configures signal "offset" as output, or returns error
274 : : * This can be omitted on input-only or output-only gpio chips.
275 : : * @get: returns value for signal "offset", 0=low, 1=high, or negative error
276 : : * @get_multiple: reads values for multiple signals defined by "mask" and
277 : : * stores them in "bits", returns 0 on success or negative error
278 : : * @set: assigns output value for signal "offset"
279 : : * @set_multiple: assigns output values for multiple signals defined by "mask"
280 : : * @set_config: optional hook for all kinds of settings. Uses the same
281 : : * packed config format as generic pinconf.
282 : : * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
283 : : * implementation may not sleep
284 : : * @dbg_show: optional routine to show contents in debugfs; default code
285 : : * will be used when this is omitted, but custom code can show extra
286 : : * state (such as pullup/pulldown configuration).
287 : : * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
288 : : * not all GPIOs are valid.
289 : : * @base: identifies the first GPIO number handled by this chip;
290 : : * or, if negative during registration, requests dynamic ID allocation.
291 : : * DEPRECATION: providing anything non-negative and nailing the base
292 : : * offset of GPIO chips is deprecated. Please pass -1 as base to
293 : : * let gpiolib select the chip base in all possible cases. We want to
294 : : * get rid of the static GPIO number space in the long run.
295 : : * @ngpio: the number of GPIOs handled by this controller; the last GPIO
296 : : * handled is (base + ngpio - 1).
297 : : * @names: if set, must be an array of strings to use as alternative
298 : : * names for the GPIOs in this chip. Any entry in the array
299 : : * may be NULL if there is no alias for the GPIO, however the
300 : : * array must be @ngpio entries long. A name can include a single printk
301 : : * format specifier for an unsigned int. It is substituted by the actual
302 : : * number of the gpio.
303 : : * @can_sleep: flag must be set iff get()/set() methods sleep, as they
304 : : * must while accessing GPIO expander chips over I2C or SPI. This
305 : : * implies that if the chip supports IRQs, these IRQs need to be threaded
306 : : * as the chip access may sleep when e.g. reading out the IRQ status
307 : : * registers.
308 : : * @read_reg: reader function for generic GPIO
309 : : * @write_reg: writer function for generic GPIO
310 : : * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
311 : : * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
312 : : * generic GPIO core. It is for internal housekeeping only.
313 : : * @reg_dat: data (in) register for generic GPIO
314 : : * @reg_set: output set register (out=high) for generic GPIO
315 : : * @reg_clr: output clear register (out=low) for generic GPIO
316 : : * @reg_dir_out: direction out setting register for generic GPIO
317 : : * @reg_dir_in: direction in setting register for generic GPIO
318 : : * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
319 : : * be read and we need to rely on out internal state tracking.
320 : : * @bgpio_bits: number of register bits used for a generic GPIO i.e.
321 : : * <register width> * 8
322 : : * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
323 : : * shadowed and real data registers writes together.
324 : : * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
325 : : * safely.
326 : : * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
327 : : * direction safely. A "1" in this word means the line is set as
328 : : * output.
329 : : *
330 : : * A gpio_chip can help platforms abstract various sources of GPIOs so
331 : : * they can all be accessed through a common programing interface.
332 : : * Example sources would be SOC controllers, FPGAs, multifunction
333 : : * chips, dedicated GPIO expanders, and so on.
334 : : *
335 : : * Each chip controls a number of signals, identified in method calls
336 : : * by "offset" values in the range 0..(@ngpio - 1). When those signals
337 : : * are referenced through calls like gpio_get_value(gpio), the offset
338 : : * is calculated by subtracting @base from the gpio number.
339 : : */
340 : : struct gpio_chip {
341 : : const char *label;
342 : : struct gpio_device *gpiodev;
343 : : struct device *parent;
344 : : struct module *owner;
345 : :
346 : : int (*request)(struct gpio_chip *chip,
347 : : unsigned offset);
348 : : void (*free)(struct gpio_chip *chip,
349 : : unsigned offset);
350 : : int (*get_direction)(struct gpio_chip *chip,
351 : : unsigned offset);
352 : : int (*direction_input)(struct gpio_chip *chip,
353 : : unsigned offset);
354 : : int (*direction_output)(struct gpio_chip *chip,
355 : : unsigned offset, int value);
356 : : int (*get)(struct gpio_chip *chip,
357 : : unsigned offset);
358 : : int (*get_multiple)(struct gpio_chip *chip,
359 : : unsigned long *mask,
360 : : unsigned long *bits);
361 : : void (*set)(struct gpio_chip *chip,
362 : : unsigned offset, int value);
363 : : void (*set_multiple)(struct gpio_chip *chip,
364 : : unsigned long *mask,
365 : : unsigned long *bits);
366 : : int (*set_config)(struct gpio_chip *chip,
367 : : unsigned offset,
368 : : unsigned long config);
369 : : int (*to_irq)(struct gpio_chip *chip,
370 : : unsigned offset);
371 : :
372 : : void (*dbg_show)(struct seq_file *s,
373 : : struct gpio_chip *chip);
374 : :
375 : : int (*init_valid_mask)(struct gpio_chip *chip,
376 : : unsigned long *valid_mask,
377 : : unsigned int ngpios);
378 : :
379 : : int base;
380 : : u16 ngpio;
381 : : const char *const *names;
382 : : bool can_sleep;
383 : :
384 : : #if IS_ENABLED(CONFIG_GPIO_GENERIC)
385 : : unsigned long (*read_reg)(void __iomem *reg);
386 : : void (*write_reg)(void __iomem *reg, unsigned long data);
387 : : bool be_bits;
388 : : void __iomem *reg_dat;
389 : : void __iomem *reg_set;
390 : : void __iomem *reg_clr;
391 : : void __iomem *reg_dir_out;
392 : : void __iomem *reg_dir_in;
393 : : bool bgpio_dir_unreadable;
394 : : int bgpio_bits;
395 : : spinlock_t bgpio_lock;
396 : : unsigned long bgpio_data;
397 : : unsigned long bgpio_dir;
398 : : #endif /* CONFIG_GPIO_GENERIC */
399 : :
400 : : #ifdef CONFIG_GPIOLIB_IRQCHIP
401 : : /*
402 : : * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
403 : : * to handle IRQs for most practical cases.
404 : : */
405 : :
406 : : /**
407 : : * @irq:
408 : : *
409 : : * Integrates interrupt chip functionality with the GPIO chip. Can be
410 : : * used to handle IRQs for most practical cases.
411 : : */
412 : : struct gpio_irq_chip irq;
413 : : #endif /* CONFIG_GPIOLIB_IRQCHIP */
414 : :
415 : : /**
416 : : * @valid_mask:
417 : : *
418 : : * If not %NULL holds bitmask of GPIOs which are valid to be used
419 : : * from the chip.
420 : : */
421 : : unsigned long *valid_mask;
422 : :
423 : : #if defined(CONFIG_OF_GPIO)
424 : : /*
425 : : * If CONFIG_OF is enabled, then all GPIO controllers described in the
426 : : * device tree automatically may have an OF translation
427 : : */
428 : :
429 : : /**
430 : : * @of_node:
431 : : *
432 : : * Pointer to a device tree node representing this GPIO controller.
433 : : */
434 : : struct device_node *of_node;
435 : :
436 : : /**
437 : : * @of_gpio_n_cells:
438 : : *
439 : : * Number of cells used to form the GPIO specifier.
440 : : */
441 : : unsigned int of_gpio_n_cells;
442 : :
443 : : /**
444 : : * @of_xlate:
445 : : *
446 : : * Callback to translate a device tree GPIO specifier into a chip-
447 : : * relative GPIO number and flags.
448 : : */
449 : : int (*of_xlate)(struct gpio_chip *gc,
450 : : const struct of_phandle_args *gpiospec, u32 *flags);
451 : : #endif /* CONFIG_OF_GPIO */
452 : : };
453 : :
454 : : extern const char *gpiochip_is_requested(struct gpio_chip *chip,
455 : : unsigned offset);
456 : :
457 : : /* add/remove chips */
458 : : extern int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
459 : : struct lock_class_key *lock_key,
460 : : struct lock_class_key *request_key);
461 : :
462 : : /**
463 : : * gpiochip_add_data() - register a gpio_chip
464 : : * @chip: the chip to register, with chip->base initialized
465 : : * @data: driver-private data associated with this chip
466 : : *
467 : : * Context: potentially before irqs will work
468 : : *
469 : : * When gpiochip_add_data() is called very early during boot, so that GPIOs
470 : : * can be freely used, the chip->parent device must be registered before
471 : : * the gpio framework's arch_initcall(). Otherwise sysfs initialization
472 : : * for GPIOs will fail rudely.
473 : : *
474 : : * gpiochip_add_data() must only be called after gpiolib initialization,
475 : : * ie after core_initcall().
476 : : *
477 : : * If chip->base is negative, this requests dynamic assignment of
478 : : * a range of valid GPIOs.
479 : : *
480 : : * Returns:
481 : : * A negative errno if the chip can't be registered, such as because the
482 : : * chip->base is invalid or already associated with a different chip.
483 : : * Otherwise it returns zero as a success code.
484 : : */
485 : : #ifdef CONFIG_LOCKDEP
486 : : #define gpiochip_add_data(chip, data) ({ \
487 : : static struct lock_class_key lock_key; \
488 : : static struct lock_class_key request_key; \
489 : : gpiochip_add_data_with_key(chip, data, &lock_key, \
490 : : &request_key); \
491 : : })
492 : : #else
493 : : #define gpiochip_add_data(chip, data) gpiochip_add_data_with_key(chip, data, NULL, NULL)
494 : : #endif /* CONFIG_LOCKDEP */
495 : :
496 : : static inline int gpiochip_add(struct gpio_chip *chip)
497 : : {
498 : 0 : return gpiochip_add_data(chip, NULL);
499 : : }
500 : : extern void gpiochip_remove(struct gpio_chip *chip);
501 : : extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
502 : : void *data);
503 : :
504 : : extern struct gpio_chip *gpiochip_find(void *data,
505 : : int (*match)(struct gpio_chip *chip, void *data));
506 : :
507 : : bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
508 : : int gpiochip_reqres_irq(struct gpio_chip *chip, unsigned int offset);
509 : : void gpiochip_relres_irq(struct gpio_chip *chip, unsigned int offset);
510 : : void gpiochip_disable_irq(struct gpio_chip *chip, unsigned int offset);
511 : : void gpiochip_enable_irq(struct gpio_chip *chip, unsigned int offset);
512 : :
513 : : /* Line status inquiry for drivers */
514 : : bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
515 : : bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
516 : :
517 : : /* Sleep persistence inquiry for drivers */
518 : : bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);
519 : : bool gpiochip_line_is_valid(const struct gpio_chip *chip, unsigned int offset);
520 : :
521 : : /* get driver data */
522 : : void *gpiochip_get_data(struct gpio_chip *chip);
523 : :
524 : : struct bgpio_pdata {
525 : : const char *label;
526 : : int base;
527 : : int ngpio;
528 : : };
529 : :
530 : : #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
531 : :
532 : : void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chip,
533 : : struct irq_fwspec *fwspec,
534 : : unsigned int parent_hwirq,
535 : : unsigned int parent_type);
536 : : void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip,
537 : : struct irq_fwspec *fwspec,
538 : : unsigned int parent_hwirq,
539 : : unsigned int parent_type);
540 : :
541 : : #else
542 : :
543 : : static inline void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chip,
544 : : struct irq_fwspec *fwspec,
545 : : unsigned int parent_hwirq,
546 : : unsigned int parent_type)
547 : : {
548 : : }
549 : :
550 : : static inline void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip,
551 : : struct irq_fwspec *fwspec,
552 : : unsigned int parent_hwirq,
553 : : unsigned int parent_type)
554 : : {
555 : : }
556 : :
557 : : #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
558 : :
559 : : int bgpio_init(struct gpio_chip *gc, struct device *dev,
560 : : unsigned long sz, void __iomem *dat, void __iomem *set,
561 : : void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
562 : : unsigned long flags);
563 : :
564 : : #define BGPIOF_BIG_ENDIAN BIT(0)
565 : : #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
566 : : #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
567 : : #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
568 : : #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
569 : : #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
570 : :
571 : : int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
572 : : irq_hw_number_t hwirq);
573 : : void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
574 : :
575 : : int gpiochip_irq_domain_activate(struct irq_domain *domain,
576 : : struct irq_data *data, bool reserve);
577 : : void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
578 : : struct irq_data *data);
579 : :
580 : : void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
581 : : struct irq_chip *irqchip,
582 : : unsigned int parent_irq,
583 : : irq_flow_handler_t parent_handler);
584 : :
585 : : void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
586 : : struct irq_chip *irqchip,
587 : : unsigned int parent_irq);
588 : :
589 : : int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
590 : : struct irq_chip *irqchip,
591 : : unsigned int first_irq,
592 : : irq_flow_handler_t handler,
593 : : unsigned int type,
594 : : bool threaded,
595 : : struct lock_class_key *lock_key,
596 : : struct lock_class_key *request_key);
597 : :
598 : : bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
599 : : unsigned int offset);
600 : :
601 : : #ifdef CONFIG_LOCKDEP
602 : :
603 : : /*
604 : : * Lockdep requires that each irqchip instance be created with a
605 : : * unique key so as to avoid unnecessary warnings. This upfront
606 : : * boilerplate static inlines provides such a key for each
607 : : * unique instance.
608 : : */
609 : : static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
610 : : struct irq_chip *irqchip,
611 : : unsigned int first_irq,
612 : : irq_flow_handler_t handler,
613 : : unsigned int type)
614 : : {
615 : : static struct lock_class_key lock_key;
616 : : static struct lock_class_key request_key;
617 : :
618 : : return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
619 : : handler, type, false,
620 : : &lock_key, &request_key);
621 : : }
622 : :
623 : : static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
624 : : struct irq_chip *irqchip,
625 : : unsigned int first_irq,
626 : : irq_flow_handler_t handler,
627 : : unsigned int type)
628 : : {
629 : :
630 : : static struct lock_class_key lock_key;
631 : : static struct lock_class_key request_key;
632 : :
633 : : return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
634 : : handler, type, true,
635 : : &lock_key, &request_key);
636 : : }
637 : : #else /* ! CONFIG_LOCKDEP */
638 : : static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
639 : : struct irq_chip *irqchip,
640 : : unsigned int first_irq,
641 : : irq_flow_handler_t handler,
642 : : unsigned int type)
643 : : {
644 : 3 : return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
645 : : handler, type, false, NULL, NULL);
646 : : }
647 : :
648 : : static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
649 : : struct irq_chip *irqchip,
650 : : unsigned int first_irq,
651 : : irq_flow_handler_t handler,
652 : : unsigned int type)
653 : : {
654 : 0 : return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
655 : : handler, type, true, NULL, NULL);
656 : : }
657 : : #endif /* CONFIG_LOCKDEP */
658 : :
659 : : int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
660 : : void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
661 : : int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
662 : : unsigned long config);
663 : :
664 : : /**
665 : : * struct gpio_pin_range - pin range controlled by a gpio chip
666 : : * @node: list for maintaining set of pin ranges, used internally
667 : : * @pctldev: pinctrl device which handles corresponding pins
668 : : * @range: actual range of pins controlled by a gpio controller
669 : : */
670 : : struct gpio_pin_range {
671 : : struct list_head node;
672 : : struct pinctrl_dev *pctldev;
673 : : struct pinctrl_gpio_range range;
674 : : };
675 : :
676 : : #ifdef CONFIG_PINCTRL
677 : :
678 : : int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
679 : : unsigned int gpio_offset, unsigned int pin_offset,
680 : : unsigned int npins);
681 : : int gpiochip_add_pingroup_range(struct gpio_chip *chip,
682 : : struct pinctrl_dev *pctldev,
683 : : unsigned int gpio_offset, const char *pin_group);
684 : : void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
685 : :
686 : : #else /* ! CONFIG_PINCTRL */
687 : :
688 : : static inline int
689 : : gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
690 : : unsigned int gpio_offset, unsigned int pin_offset,
691 : : unsigned int npins)
692 : : {
693 : : return 0;
694 : : }
695 : : static inline int
696 : : gpiochip_add_pingroup_range(struct gpio_chip *chip,
697 : : struct pinctrl_dev *pctldev,
698 : : unsigned int gpio_offset, const char *pin_group)
699 : : {
700 : : return 0;
701 : : }
702 : :
703 : : static inline void
704 : : gpiochip_remove_pin_ranges(struct gpio_chip *chip)
705 : : {
706 : : }
707 : :
708 : : #endif /* CONFIG_PINCTRL */
709 : :
710 : : struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
711 : : const char *label,
712 : : enum gpio_lookup_flags lflags,
713 : : enum gpiod_flags dflags);
714 : : void gpiochip_free_own_desc(struct gpio_desc *desc);
715 : :
716 : : void devprop_gpiochip_set_names(struct gpio_chip *chip,
717 : : const struct fwnode_handle *fwnode);
718 : :
719 : : #ifdef CONFIG_GPIOLIB
720 : :
721 : : /* lock/unlock as IRQ */
722 : : int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
723 : : void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
724 : :
725 : :
726 : : struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
727 : :
728 : : #else /* CONFIG_GPIOLIB */
729 : :
730 : : static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
731 : : {
732 : : /* GPIO can never have been requested */
733 : : WARN_ON(1);
734 : : return ERR_PTR(-ENODEV);
735 : : }
736 : :
737 : : static inline int gpiochip_lock_as_irq(struct gpio_chip *chip,
738 : : unsigned int offset)
739 : : {
740 : : WARN_ON(1);
741 : : return -EINVAL;
742 : : }
743 : :
744 : : static inline void gpiochip_unlock_as_irq(struct gpio_chip *chip,
745 : : unsigned int offset)
746 : : {
747 : : WARN_ON(1);
748 : : }
749 : : #endif /* CONFIG_GPIOLIB */
750 : :
751 : : #endif /* __LINUX_GPIO_DRIVER_H */
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