============================== Sample 1 ============================== ASM: ;************************************************************************************************************************************************************ ;* FUNCTION * ;************************************************************************************************************************************************************ ;undefined QCoreApplication_quit(void) JMP .plt:::QCoreApplication::quit ?? 66h f Actual src: void QCoreApplication_quit() { QCoreApplication::quit(); } Predicted src: void QStyleOptionViewItem_quit(QStyleOptionViewItemH handle) { ((QStyleOptionViewItem *)handle)->quit(); } ============================== Sample 2 ============================== ASM: ;************************************************************************************************************************************************************ ;* FUNCTION * ;************************************************************************************************************************************************************ ;undefined fcml_tf_env_memory_alloc_handler_counter() ADD dword ptr [.bss:counter],0x1 JMP qword ptr [.bss:default_alloc] ?? 0Fh Actual src: fcml_ptr fcml_tf_env_memory_alloc_handler_counter( fcml_usize size ) { counter += 1; return default_alloc( size ); } Predicted src: void alloc_memory_alloc_handler (void) { memalloc_memory_alloc_memory (); } ============================== Sample 3 ============================== ASM: ;************************************************************************************************************************************************************ ;* FUNCTION * ;************************************************************************************************************************************************************ ;undefined uniDRICreateContext() MOV EDX,dword ptr [RDX + 0x8] JMP uniDRICreateContextWithConfig ;undefined uniDRICreateContextWithCon... ?? 0Fh Actual src: Bool uniDRICreateContext(dpy, screen, visual, context, hHWContext) Display *dpy; int screen; Visual *visual; XID *context; drm_context_t *hHWContext; { return uniDRICreateContextWithConfig(dpy, screen, visual->visualid, context, hHWContext); } Predicted src: static void ConfigConfig(Widget w, XEvent *event, String *params, Cardinal *num_params) { configConfigConfigConfig(w, event, params, num_params); } ============================== Sample 4 ============================== ASM: ;************************************************************************************************************************************************************ ;* FUNCTION * ;************************************************************************************************************************************************************ ;undefined op_edc0_22_ff() PUSH RBX MOV EBX,EDI MOV EDI,0x2 MOV dword ptr [.bss:OpcodeFamily],0x5d AND EBX,0x7 MOV dword ptr [.bss:CurrentInstrCycles],0x8 CALL get_word_030_prefetch ;undefined get_word_030_prefetch() MOV ESI,EAX TEST AH,0x8 JZ LAB_009bbe18 SAR AX,0x6 LEA R9,[.bss:regs] AND EAX,0x7 MOV EDX,dword ptr [R9 + RAX*0x4]=>.bss:regs MOV ECX,EDX AND ECX,0x1f LAB_009bbd46: TEST SIL,0x20 JZ LAB_009bbe00 MOV EAX,ESI AND EAX,0x7 MOV R8D,dword ptr [R9 + RAX*0x4]=>.bss:regs SUB R8D,0x1 AND R8D,0x1f ADD R8D,0x1 LAB_009bbd65: MOV EAX,dword ptr [R9 + RBX*0x4]=>.bss:regs ROL EAX,CL MOV ECX,0x20 MOV EDI,EAX SHR EAX,0x1f SUB ECX,R8D SHL EAX,0xf SHR EDI,CL MOV ECX,EAX MOV EAX,dword ptr [.bss:regflags] AND AH,0x3f OR EAX,ECX XOR ECX,ECX TEST EDI,EDI SETZ CL SHL ECX,0xe OR EAX,ECX LEA ECX,[R8 + -0x1] AND EAX,0xfffffefe MOV dword ptr [.bss:regflags],EAX MOV EAX,0x1 SHL EAX,CL TEST EAX,EAX JNZ LAB_009bbdbf JMP LAB_009bbdc3 ?? 66h f ?? 0Fh ?? 1Fh ?? 44h D ?? 00h ?? 00h LAB_009bbdb8: ADD EDX,0x1 SHR EAX,1 JZ LAB_009bbdc3 LAB_009bbdbf: TEST EDI,EAX JZ LAB_009bbdb8 LAB_009bbdc3: SAR SI,0xc MOV EAX,dword ptr [.bss:regs[188]] MOV EDI,0x4 AND ESI,0x7 MOV dword ptr [R9 + RSI*0x4]=>.bss:regs,EDX MOV dword ptr [.bss:regs[184]],EAX CALL get_word_030_prefetch ;undefined get_word_030_prefetch() ADD dword ptr [.bss:regs[64]],0x4 POP RBX MOV word ptr [.bss:regs[104]],AX MOV EAX,0x1000 RET ?? 0Fh ?? 1Fh ?? 80h ?? 00h ?? 00h ?? 00h ?? 00h LAB_009bbe00: LEA R8D,[RSI + 0x1f] AND R8D,0x1f ADD R8D,0x1 JMP LAB_009bbd65 ?? 0Fh ?? 1Fh ?? 80h ?? 00h ?? 00h ?? 00h ?? 00h LAB_009bbe18: MOV ECX,EAX LEA R9,[.bss:regs] SAR CX,0x6 AND ECX,0x1f MOV EDX,ECX JMP LAB_009bbd46 ?? 90h Actual src: uae_u32 REGPARAM2 op_edc0_22_ff(uae_u32 opcode) { int count_cycles = 0; uae_u32 real_opcode = opcode; uae_u32 dstreg = real_opcode & 7; OpcodeFamily = 93; CurrentInstrCycles = 8; uae_s16 extra = get_word_030_prefetch(2); uae_u32 bdata[2]; uae_s32 offset = extra & 0x800? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f; int width = (((extra & 0x20? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); { uae_u32 mask = 1 << (width - 1); while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }} m68k_dreg(regs, (extra >> 12) & 7) = offset2; ipl_fetch(); regs.irc = get_word_030_prefetch(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } Predicted src: uae_u32 REGPARAM2 op_e1f0_22_ff(uae_u32 opcode) { int count_cycles = 0; uae_u32 real_opcode = opcode; uae_u32 srcreg = (real_opcode & 7); uae_u32 dstreg = (real_opcode >> 9) & 7; OpcodeFamily = 30; CurrentInstrCycles = 12; uaecptr srca; m68k_incpci(2); uaecptr tmppc = m68k_getpci(); srca = x_get_disp_ea_020(tmppc, 0); uae_s32 src = x_get_long(srca); uae_s32 dst = m68k_dreg(regs, dstreg); uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src)); int flgs = ((uae_s32)(src)) < 0; int flgo = ((uae_s32)(dst)) < 0; int flgn = ((uae_s32)(newv)) < 0; SET_ZFLG(((uae_s32)(newv)) == 0); SET_VFLG((flgs ^ flgo) & (flgn ^ flgo)); SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst))); COPY_CARRY(); SET_NFLG(flgn!= 0); ipl_fetch(); regs.irc = get_word_030_prefetch(0); m68k_dreg(regs, dstreg) = (newv); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } ============================== Sample 5 ============================== ASM: ;************************************************************************************************************************************************************ ;* FUNCTION * ;************************************************************************************************************************************************************ ;undefined mdjvu_matcher_options_destroy() JMP .plt:::free ?? 66h f Actual src: void mdjvu_matcher_options_destroy(mdjvu_matcher_options_t opt) { FREE((Options *) opt); } Predicted src: void md_options_destroy(md_options_t *options) { free(options); }